- Jul 18, 2020
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Vadim Kaushan authored
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bors[bot] authored
65: Update `riscv` crate to version 0.6 r=Disasm a=luojia65 This pull request solves a probable version conflict between latest `riscv` and `riscv-rt`. The MSRV is also updated to 1.42.0, since the 0.6.0 version of `riscv` crate requires 1.42.0: [link](https://github.com/rust-embedded/riscv/blob/6392fa9520b042bd559b00b9c7131b6de4189f89/CHANGELOG.md#changed ). This pull request also includes a small typo fix in changelog file. Co-authored-by:
luojia65 <me@luojia.cc>
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luojia65 authored
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- Jul 16, 2020
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bors[bot] authored
63: Release v0.7.2 r=almindor a=Disasm Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Vadim Kaushan authored
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bors[bot] authored
61: Update link.x r=almindor a=richardeoin Similar to #38, riscv compilers may also generate 'small ro data' `.srodata` sections. This doesn't appear to be well documented, but see [this blog post](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain ) for small amount of context. Co-authored-by:
Richard Meadows <962920+richardeoin@users.noreply.github.com>
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Richard Meadows authored
Similar to #38, riscv compilers may also generate 'small ro data' `.srodata` sections. This doesn't appear to be well documented, but see [this blog post](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain) for small amount of context.
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- Jul 15, 2020
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bors[bot] authored
62: Preserve .eh_frame and .eh_frame_hdr r=almindor a=Disasm Preserving the `.eh_frame` section improves gdb stack traces on nightly. Preserving the `.eh_frame_hdr` section fixes the linker problem `rust-lld: error: no memory region specified for section '.eh_frame_hdr'` introduced in https://github.com/rust-lang/rust/pull/73564 Co-authored-by:
Vadim Kaushan <admin@disasm.info>
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Vadim Kaushan authored
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Vadim Kaushan authored
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- Jun 02, 2020
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bors[bot] authored
59: Release v0.7.1 r=Disasm a=khrs Co-authored-by:Karol Harasim <karol.harasim@gmail.com>
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Karol Harasim authored
Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Karol Harasim authored
Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Karol Harasim authored
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bors[bot] authored
58: Add hook to initialize custom interrupt controllers. r=Disasm a=khrs Co-authored-by:Karol Harasim <karol.harasim@gmail.com>
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Karol Harasim authored
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Karol Harasim authored
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Karol Harasim authored
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Karol Harasim authored
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Karol Harasim authored
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Karol Harasim authored
Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Karol Harasim authored
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Karol Harasim authored
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bors[bot] authored
57: Surround use of absolute address with "norelax" r=Disasm a=laanwj This prevents an unsupported `R_RISCV_ALIGN` relocation from being generated by disabling link-time relaxing for the appropriate part. Fixes #55. Co-authored-by:Wladimir J. van der Laan <laanwj@protonmail.com>
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Wladimir J. van der Laan authored
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Wladimir J. van der Laan authored
This prevents an unsupported `R_RISCV_ALIGN` relocation from being generated by disabling link-time relaxing for the appropriate part. Fixes #55.
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- Jun 01, 2020
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bors[bot] authored
56: Exception handler may return r=Disasm a=laanwj We need exceptions to be able to return. For example, after fixing the issue that caused them in the first place (e.g. paging), or after emulating missing instructions and possibly updating `mepc`. Co-authored-by:Wladimir J. van der Laan <laanwj@protonmail.com>
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Wladimir J. van der Laan authored
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- May 17, 2020
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bors[bot] authored
54: Check code style on CI r=almindor a=Disasm Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Vadim Kaushan authored
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bors[bot] authored
53: fix rust fmt to not mangle externs r=Disasm a=almindor Cargo fmt mangled all the `extern "Rust"` cases, this fixes it and cleans up the code. Co-authored-by:Ales Katona <ales@katona.me>
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Ales Katona authored
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bors[bot] authored
52: Only checking for necessary extensions when linking, made debug information location-independent r=almindor a=ilya-epifanov Regarding the debug information: ```diff 1c1 < In archive src/oss/riscv-rt-orig/bin/riscv32i-unknown-none-elf.a: --- > In archive src/oss/riscv-rt/bin/riscv32i-unknown-none-elf.a: 335,336c335,336 < <18> DW_AT_comp_dir : (indirect string, offset: 0x6): /home/disasm/dev/rust/embedded/workspace/riscv-rt < <1c> DW_AT_producer : (indirect string, offset: 0x38): GNU AS 2.32 --- > <18> DW_AT_comp_dir : (indirect string, offset: 0x6): /riscv-rt > <1c> DW_AT_producer : (indirect string, offset: 0x10): GNU AS 2.34 367,371c367,368 < 0x00000000 61736d2e 53002f68 6f6d652f 64697361 asm.S./home/disa < 0x00000010 736d2f64 65762f72 7573742f 656d6265 sm/dev/rust/embe < 0x00000020 64646564 2f776f72 6b737061 63652f72 dded/workspace/r < 0x00000030 69736376 2d727400 474e5520 41532032 iscv-rt.GNU AS 2 < 0x00000040 2e333200 .32. --- > 0x00000000 61736d2e 53002f72 69736376 2d727400 asm.S./riscv-rt. > 0x00000010 474e5520 41532032 2e333400 GNU AS 2.34. 386c383 < Version: 1 --- > Version: 3 ``` Versions are still different, but at least the build paths are independent from the build environment. Co-authored-by:Ilya Epifanov <elijah.epifanov@gmail.com>
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bors[bot] authored
51: CI fixes and improvements r=almindor a=Disasm Co-authored-by:Vadim Kaushan <admin@disasm.info>
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- May 16, 2020
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Ilya Epifanov authored
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Ilya Epifanov authored
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- Apr 22, 2020
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Vadim Kaushan authored
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bors[bot] authored
50: Document MSRV on README r=Disasm a=eldruin See: https://github.com/rust-embedded/wg/issues/445 Co-authored-by:
Diego Barrios Romero <eldruin@gmail.com>
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Vadim Kaushan authored
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Vadim Kaushan authored
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