30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>

31: Add more CSRs r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

26: Fix Misa::has_extension() r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

25: Rename RISCV to RISC-V in documentation r=Disasm a=medusacle

More common name for the CPU architecture 😄

  Also update the copyright year.

Probably, if this is merged, you'd want to update the project description as well.

Co-authored-by: mara <vmedea@protonmail.com>

24: Add FS and XS fields, fix incorrect field setting, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

23: Add fcsr register r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

22: Update CI, add MSRV policy r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>