30: Fix docs, add MSRV policy, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

27: Add 'entry' and 'pre_init' attributes r=dvc94ch a=Disasm

Implementation is based on [`cortex-m-rt-macros`](https://github.com/rust-embedded/cortex-m-rt/tree/master/macros) code.

This implementation has been changed to make `static mut` unsafe inside entry point and different handlers.

Related: https://github.com/rust-embedded/riscv-rt/pull/20



Co-authored-by: Vadim Kaushan <admin@disasm.info>

28: Add support for 64-bit targets r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

23: Fix _start_trap alignment r=dvc94ch a=Disasm

Based on this proposal: https://github.com/rust-embedded/riscv-rt/pull/22#issuecomment-466307711



Co-authored-by: Vadim Kaushan <admin@disasm.info>

22: Fix _start_trap address calculation r=danc86 a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

21: Add team e-mail to authors r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

19: Remove the unused 'const-fn' feature r=dvc94ch a=Disasm

`const-fn` feature for `riscv` is no longer present: https://github.com/rust-embedded/riscv/pull/18



cc @rust-embedded/riscv

Co-authored-by: Vadim Kaushan <admin@disasm.info>

18: Update docs and bump version r=dvc94ch a=Disasm

cc @rust-embedded/riscv 

Co-authored-by: Vadim Kaushan <admin@disasm.info>