Merge #68

68: Bug fix for interrupt bit in `scause::set` r=Disasm a=luojia65

This pull request includes a bug fix. On RISC-V's cause register, first bit means is this cause an interrupt. The code before made a mistake to or an one bit when exception. After this fix, it correctly or an one bit when interrupt.

Related to https://github.com/luojia65/rustsbi/issues/10

. Thank you @wyfcyx

Co-authored-by: luojia65 <me@luojia.cc>