98: Convert default_setup_interrupts into a Rust function r=dkhayes117 a=Disasm

First step towards a fully inline-asm `riscv-rt`.

Co-authored-by: Vadim Kaushan <admin@disasm.info>

97: Release v0.9.0 r=dkhayes117 a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

96: Add missing changelog entries r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

95: Pass a0..a2 to main() r=almindor a=Disasm

This PR delivers arguments stored in a0..a2 to `main`.

Fixes https://github.com/rust-embedded/riscv-rt/issues/92



Tested with:
* build the `empty` example for `riscv64imac-unknown-none-elf` with a memory file which puts everything to `0x80000000`
* run `qemu-system-riscv64 -nographic -machine virt -bios target/riscv64imac-unknown-none-elf/release/examples/empty -s -S`
* connect to qemu with gdb (`target remote :1234`)
* set breakpoint to main (`b main`)
* resume execution (`continue`)
* inspect registers (`info registers`)
```
a0             0x0	0
a1             0x87000000	2264924160
a2             0x1028	4136
```
* check header (`x/xw 0x87000000`)
```
0x87000000:	0xedfe0dd0
```

Co-authored-by: Vadim Kaushan <admin@disasm.info>

93: Rerun the build script if the bin/{}.a archive has changed r=Disasm a=SimonSapin

This PR also includes some drive-by cleanup commits, but the last one is what’s significant. This bit me when trying to make changes to `asm.S` and rebuilding with `./assemble.sh`.

(By the way, I get ``Assembler messages: Fatal error: invalid -march= option: `rv32i'`` when running that script on Arch Linux despite installing a GNU toolchain for RISC-V. Instead I’m now using an Ubuntu 20.04 container to run it, since that’s what CI does for `./check-blobs.sh`.)

Co-authored-by: Simon Sapin <simon.sapin@exyr.org>

https://doc.rust-lang.org/cargo/reference/build-scripts.html#cargorerun-if-changedpath

91: Don't use a random hash ident, instead use the crate prefixed symbol r=almindor a=MabezDev

This is what cortex-m land is doing. This was initially discovered to be an issue when implementing unwinding in riscv probe-rs, the dwarf info shows the hashed symbol name which is a bit weird, this makes it more clear what the symbol actually is.

Co-authored-by: Scott Mabin <scott@mabez.dev>

90: Update copyright years r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

89: Fix links in changelog r=dkhayes117 a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

88: Update riscv to 0.8 and remove inline-asm feature r=almindor a=taiki-e

This also updates MSRV to 1.59.

Co-authored-by: Taiki Endo <te316e89@gmail.com>

This also updates MSRV to 1.59.

87: release v0.8.1 r=Disasm a=almindor

Release v0.8.1 to fix #85 

Co-authored-by: Ales Katona <ales@katona.me>

86: Update CHANGELOG.md r=almindor a=parkero

Adds currently unreleased changes for #85 

Co-authored-by: parkero <7399144+parkero@users.noreply.github.com>

81: Trap handler override improvments r=almindor a=MabezDev

* Add ability to override trap handling mechanism
  * Previously, `_start_trap` was marked as weak, which when compiled
    into a static archive, that information is ignored.
  * Now by default we `PROVIDE` the default trap handler, if another one
    has not been specified from another crate.
* Mark the fields of `Vector` public, for use outside of `riscv-rt`

Co-authored-by: Scott Mabin <scott@mabez.dev>

* Add ability to override trap handling mechanism
  * Previously, `_start_trap` was marked as weak, which when compiled
    into a static archive, that information is ignored.
  * Now by default we `PROVIDE` the default trap handler, if another one
    has not been specified from another crate.
* Mark the fields of `Vector` public, for use outside of `riscv-rt`

79: update to riscv 0.7 r=almindor a=smsxgli

hi everyone, I am a new guy with both github, rust and riscv, and this is my first PR, so if I miss something or do something wrong, please let me know (and forgive my poor english, since I am not a native speaker).
crate `riscv` v0.7 solved link error about [`different hardware float abi`](https://github.com/rust-embedded/riscv/issues/85

), but riscv-rt still depend on `riscv` v0.6.

Co-authored-by: smsxgli <smsxgli@gmail.com>

77: use --target for CI checks r=Disasm a=almindor



Co-authored-by: Ales Katona <ales@katona.me>

74: [NFC] Fix typo 'suppoted' -> 'supported' r=Disasm a=jmerdich

Interested in using this crate and saw this typo when browsing the docs.

Co-authored-by: Jake Merdich <jake@merdich.com>

73: Fix link to RISC-V team in wg repo r=Disasm a=hasheddan

Fixes link to properly direct to heading in wg repo README.md.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>

Co-authored-by: hasheddan <georgedanielmangum@gmail.com>

76: switch to Github Actions for CI r=Disasm a=almindor



Co-authored-by: Ales Katona <ales@katona.me>

Interested in using this crate and saw this typo when browsing the docs.

Fixes link to properly direct to heading in wg repo README.md.

Signed-off-by: hasheddan <georgedanielmangum@gmail.com>

67: Update dependencies of riscv-rt-macros r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>