- Nov 28, 2023
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Román Cárdenas authored
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- Nov 10, 2023
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Chien Wong authored
Signed-off-by:Chien Wong <m@xv97.com>
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Chien Wong authored
Signed-off-by: -
Kevin Vigor authored
Don't bother checking hart ID on startup in single-hart mode. Allows use of cores with unusual mhartid values and saves a few instructions.
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- Nov 09, 2023
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Román Cárdenas authored
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- Oct 03, 2023
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Román Cárdenas authored
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Román Cárdenas authored
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- Sep 29, 2023
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Gijs Burghoorn authored
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- Aug 11, 2023
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Román Cárdenas authored
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- Jul 09, 2023
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Román Cárdenas authored
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- Jul 04, 2023
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Román Cárdenas authored
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- Jan 19, 2023
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Ales Katona authored
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Ales Katona authored
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- Dec 26, 2022
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tfx2001 authored
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- Nov 05, 2022
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Ales Katona authored
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- Sep 17, 2022
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Pablo Graubner authored
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Pablo Graubner authored
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- Sep 09, 2022
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Jan Niehusmann authored
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- Jul 01, 2022
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Vadim Kaushan authored
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- Jun 30, 2022
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Vadim Kaushan authored
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- Jun 11, 2022
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Scott Mabin authored
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- Apr 23, 2022
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Vadim Kaushan authored
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Taiki Endo authored
This also updates MSRV to 1.59.
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- Jan 27, 2022
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Ales Katona authored
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- Jan 26, 2022
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parkero authored
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- Jul 18, 2020
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Vadim Kaushan authored
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luojia65 authored
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- Jul 16, 2020
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Vadim Kaushan authored
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Richard Meadows authored
Similar to #38, riscv compilers may also generate 'small ro data' `.srodata` sections. This doesn't appear to be well documented, but see [this blog post](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain) for small amount of context.
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- Jul 15, 2020
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Vadim Kaushan authored
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- Jun 02, 2020
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Karol Harasim authored
Co-authored-by:Vadim Kaushan <admin@disasm.info>
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Karol Harasim authored
Co-authored-by: -
Karol Harasim authored
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Karol Harasim authored
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- Mar 10, 2020
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Vadim Kaushan authored
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Vadim Kaushan authored
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