Add feature single-hart

Signed-off-by: Chien Wong <m@xv97.com>

Use inline assembly instead of pre-compiled blobs

Fix oor branch via linking

Temporary fix for OOR branch

Move towards GHMQ

110: fix: avoid rust-analyzer snake case warning r=almindor a=sethp

It seems that rust-analyzer needs to operate over the expanded text of the proc macro (in order to e.g. support completion in the function body, see #11014 for way more details), so it "sees" the non-snake-case name emitted by riscv-rt's `entry` here.

Without this change, rust-analyzer will show a "weak warning" on invocations of `#[entry]` with the text:

```
Function `__risc_v_rt__main` should have snake_case name, e.g. `__risc_v_rt_main`
```

Co-authored-by: sethp <seth@codecopse.net>

It seems that rust-analyzer needs to operate over the expanded text of the proc macro (in order to e.g. support completion in the function body, see #11014 for way more details), so it "sees" the non-snake-case name emitted by riscv-rt's `entry` here.

Without this change, rust-analyzer will show a "weak warning" on invocations of `#[entry]` with the text:

```
Function `__risc_v_rt__main` should have snake_case name, e.g. `__risc_v_rt_main`
```

109: release v0.11.0 with riscv CS fix r=dkhayes117 a=almindor

Updates riscv to 0.10.1 with the critical section fix

Co-authored-by: Ales Katona <ales@katona.me>

108: update to riscv 0.10 r=dkhayes117 a=tfx2001

In `svd2rust` 0.24.2, require `critial-section` feature of `riscv` 0.10.0 to use the `Peripheral::take()`. So update `riscv` to 0.10 avoid link error.

```text
  = note: rust-lld: error: undefined symbol: _critical_section_1_0_release
          >>> referenced by lib.rs:197 (C:\***\.cargo\registry\src\github.com-1ecc6299db9ec823\critical-section-1.1.1\src/lib.rs:197)
          >>>               C:\***\target\riscv32imac-unknown-none-elf\debug\deps\blink-38e172683ad1eb45.21kbt3gcucoa48u6.rcgu.o:(core::ptr::drop_in_place$LT$critical_section..with..Guard$GT$::h47fa1a207a83c94b)

          rust-lld: error: undefined symbol: _critical_section_1_0_acquire
          >>> referenced by lib.rs:180 (C:\***\.cargo\registry\src\github.com-1ecc6299db9ec823\critical-section-1.1.1\src/lib.rs:180)
          >>>               C:\***\target\riscv32imac-unknown-none-elf\debug\deps\blink-38e172683ad1eb45.54bke7unpav17a81.rcgu.o:(critical_section::with::h3ba86eebd468f130)
```

Co-authored-by: tfx2001 <tfx2001@outlook.com>

105: release v0.10.0 r=Disasm a=almindor

Release latest master as `v0.10.0` to fix #102 properly

Co-authored-by: Ales Katona <ales@katona.me>

104: SBI mode r=almindor a=pgraubner

Introducing Supervisor Binary Interface (SBI) compatibility as a build-time feature. Main goal is to allow riscv-rt based implementations to be bootstrapped by a SBI-firmware (like in `qemu-system-riscv64`).

* Introduce compiler switches for assembly in order to switch between machine mode / supervisor mode
* Introduce cargo feature for conditional compilation
* Patch lib.rs for supervisor-mode compatibility

The only interface this PR is braking is `mp_hook`, which needs a mhartid replacement for smode. The hart id is passed by the caller.
Tested with `qemu-system-riscv64`.

See also documentation/features/sbi for further implementation details.

Co-authored-by: Pablo Graubner <2234137+pgraubner@users.noreply.github.com>

103: Remove superfluous parentheses from link.x r=almindor a=jannic

Fixes #102

Co-authored-by: Jan Niehusmann <jan@gondor.com>

Fixes #102