[*] application closing logic cleanup and optimization

[!] Bug in icache fixed
[+] Unaligned load/store exception generation added
[*] 60 MHz zephyr -> 40 MHz
[*] markdown update

[*] Testing Zephyr 1.6 on functional model. SystemC and VHDL in progress

[!] Fix bug in axictrl that was cause zero value reading from memory using debugger

[+] Add registers modification capability from GUI
[!] Fix bug in 'help' command

[+] markdown updated with new top level picture

[*] Preparing to significant update of the AXI interconnect

[*] RIVER branch predictor improved by detecting 'ret' and 'jal' instructions that add +5 percentage to CPI.
[*] readme with RIVER benchmark result updated

[*] SystemC RIVER: several tests instructions executed: registers hazard and memory data load (LD) tested. DCache not entirely implemented yet.

[+] added new debugge demo
[+] empty project of the SystemC CPU "River" added.