RISC-V: Prohibit relaxing the initial gp generation

I've added an additional linker relaxation that relaxes two instruction
pc-relative sequences to one instruction gp relative sequences when
possible.  This sequence now optimizes the initial gp generation to

  mv gp, gp

which is obviously bogus.  The fix is to disable relaxations when
setting up gp, preventing the linker from relaxing away this setup code.