RISCV: Disable timer interrupt in handler to fix nohz.

The timer interrupt pending bit is cleared in bbl while
reprogramming the timer. This works fine unless we are
in nohz mode. In nohz mode, the timer is not reprogrammed.
Thus, the pending bits are not cleared leading to continuous
timer interrupt firing and cpu stalls.

Disable timer interrupt in interrupt handler to ignore
the pending bit until next interrupt. Timer interrupt
is enabled again before next timer event is set.

The details of the stalls can be found in
https://github.com/riscv/riscv-linux/issues/127

Other possible ideas discussion:
https://github.com/riscv/riscv-pk/pull/108



Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>