pcie-xilinx: Work-around for hardware DMA limit (32 bits)
This PCIe bridge only has a 32 bit bus master interface, thus truncating
the DMA capability of all PCIe devices attached beneath it. This caps
the child device capability so that these devices work on systems with
physical memory beyond the 4GiB threshold.
Signed-off-by:
Palmer Dabbelt <palmer@dabbelt.com>
parent
f7d21ab9
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