The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction,
with the following differences:
 * FCVTMOD.W.D always rounds towards zero.
 * Bits 31:0 are taken from the rounded, unbounded two's complement result,
   then sign-extended to XLEN bits and written to integer register rd.
 * Positive infinity, negative infinity and NaN are converted to zero.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S
instructions, excpet that quiet NaN inputs do not cause the invalid
operation exception flag to be set.

FLEQ.H and FLTQ.H instructions are analogously defined to operate on
half-precision numbers.

FLEQ.D and FLTQ.D instructions are analogously defined to operate on
double-precision numbers.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FMVH.X.D instruction is available for RV32 only and moves bits 63:32
of floating-point register rs1 into integer register rd.

FMVP.D.X instruction is available for RV32 only and moves a
double-precision number from a pair of integer registers into a
floating-point register. Integer registers rs1 and rs2 supply bits
31:0 and 63:32, respectively.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FROUND.H instruction rounds the half-precision floating-point
number in floating-point register rs1 and writes that integer,
represented as a half-precision floating-point number to
floating-point register rd while:
* Zero and infinite inputs are copied to rd unmodified.
* NaN inputs cause the invalid operation exception flag to be set.

Instructions FROUND.S and FROUND.D are analogously defined to operate
on single-precision numbers(FROUND.S) and double-precision numbers(FROUND.D)

FROUNDNX.H instruction is defined similarly, but also sets the inexact
exception flag if the input differs from the rounded result and is not
NaN.

Instructions FROUNDNX.S and FROUNDNX.D are analogously defined to operate
on single-precision numbers(FROUNDNX.S) and double-precision numbers(FROUNDNX.D)

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FMINM.H and FMAXM.H provide similar functionality to FMIN.H and
FMAX.H, differing only in ther NaN-handling:
 * FMIN/FMAX return a canonical NaN only if both operands are a NaN
 * FMINM/FMAXM return a canonical NaN if any operand is a NaN

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FMINM.D and FMAXM.D provide similar functionality to FMIN.D and
FMAX.D, differing only in ther NaN-handling:
 * FMIN/FMAX return a canonical NaN only if both operands are a NaN
 * FMINM/FMAXM return a canonical NaN if any operand is a NaN

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FLI.H & FLI.D provides support for loading one of 32 immediate
floating-point constants(16-bit for FLI.H, 64-bit for FLI.D) with
a single instruction using a 32-entry lookup table.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FMINM.S and FMAXM.S provide similar functionality to FMIN.S and
FMAX.S, differing only in their NaN-handling:
 * FMIN/FMAX return a canonical NaN only if both operands are a NaN
 * FMINM/FMAXM return a canonical Nan if any operand is a NaN

Consequently, the implementation is identical to FMIN/FMAX with only
the NaN-related tests changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

FLI.S provides support for loading one of 32 immediate floating-point
constants (so it is not really a 'load immediate', but rather a 'load
constant') with a single instruction using a 32-entry lookup table.

Lacking further guidance in the specification, we disallow this
instruction for Xfinx.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

To support the implementation of the Zfa extension in SAIL, this
creates the necessary infrastructure (i.e., a file to hold it, and the
existence macro), preparing the tree for the Zfa implementation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Ubuntu 18.04 is being sunset.

Sail tries to check for pattern match completeness and issues warnings
but this often gives false positives: see discussion at
https://github.com/rems-project/sail/issues/191 .  To suppress these
we add a wildcard case that raises an internal error.  There is
effectively no behaviour change as these would previously have
resulted in a match error at runtime and they should be unreachable
anyway.

At the same time we change the DOUBLE case in memory access paths to
allow for xlen > 64.

Following discussion on the PR I also changed internal_error to take a
file and line number as an argument to aid with debugging.

Fixes: https://github.com/riscv/sail-riscv/issues/194

This can now be found in the Sail repository.
Includes an update to sail-riscv.install

Revert "added 3 new command line switches (plus functionality):  -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)" (#220)

Reverts #219. Merged without code review and with many issues.

This reverts commit 43b81eaf.

added 3 new command line switches (plus functionality):  -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)

* added 3 command-line switches:  -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond

* example commit

* fixed some type warnings/errors (between int/bool)

Previously the decoding hook (`ext_post_decode_hook`) allowed models to
override the decoded `ast`. However, this is not sufficient if model
extension changes interpretation of fields. Additionally, the assembly
printing would always print assembly for the "baseline decode" which
resulted in incorrect trace output in the sail-cheri-riscv model.

With the new hook models can implement ext_decode()/ext_decode_compressed()
to return an `ast` and for encodings that are not adjusted fall back to
the default `encdec`/`encdec_compressed`.

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

This option causes handle_illegal to pass instbits as the value to set
for xtval, but instbits is never set so it ends up being 0 just as if
the option was never enabled. Fix this by initialising instbits during
fetch; we could make this conditional on whether the option is enabled
but that seems unnecessary and introduces tighter coupling.

Note that this option appears to have always been broken; when it was
originally added, instbits was only written two in two cases which were
both dead code and later removed in eb176111.

Closes: #173

After the last commit -fcommon is no longer required.

This reverts commit ffea7a39.

The sail C code generator will emit definions for these structs. The
duplicate definition linker error were worked around by adding -fcommon
in ffea7a39. This commit fixes the
underlying issue by declaring the variables as `extern`.

Merged after code review. Thanks everybody for helping.

* test: Ignore generated XML output

* run_tests: Build RVFI emulators too

Can't run tests with them though as they're built for direct instruction
injection (RVFI-DII) via an instruction stream over a network socket,
not fetching instructions from memory, so this remains just a build
test.

* run_tests/run_fp_tests: Print summary and give meaningful exit code

* run_tests/run_fp_tests: Include tests and failures in top-level XML entity

* run_tests/run_fp_tests: Use failure not error for XML output

The former is the standard tag for normal test failures, the latter is
for catastrophic things like test harness errors.

* Run ISA tests in CI

pull-requests ideally come with an explanation how the correctness of
the PR was established.

These are intended to deal with much of the low-hanging fruit; plenty of
room for improvement exists.

The order used for wildcard is not deterministic and varies between
systems. Sorting ensures the diffs are easy to inspect going forwards.

Closes: #142

NB: Smstateen support is missing in the model so enabling the Zfinx
extension provides an architectural covert channel via FCSR if
privileged software is not aware of Zfinx's existence.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

Co-authored-by: Ibrahim Abu Kharmeh <abukharmeh@gmail.com>

This reverts commit c5e62ea4.

* Adds Zfinx enable flag

* Hardwire misa.{f,d} and mstats.FS to 0

* Moving nan boxing functions to fdext_reg

* Swaps register names for floating point instructions

Adds new mapping to swap register names, and use it in all assembly clauses

* Disable Floating point loads, stores and moves

* Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points

Changes register accessed for floating point instructions and modify nan boxing functions for zfinx

* Formatting

Remove couple of misplaced whitespace, unnecessary parens

* Fix inconsistent indentation in insts_dext file

* Fix spacing in fdext_regs

* Remove redundant comparasion with true/ false

* Constistant tuples spacing and removes couple of unnecessary parens.

* Consistent functions declaration & calls spacing and removes couple of unnecessary parens.

* Consistent spacing and removes couple of unnecessary comparasion with true/false

* Make spacing consistent

* Remove checks from execution stage

* Add checks to encdec stage

Trying to make the behavior of aesks1i easier to understand, and more
obviously correspond to the specification.

- Ensure that the aes_decode_rcon function only accepts valid values, plus
  add comments.

- Re-name operands to aesks1i rcon -> rnum to be in line with the specification

- Re-structure the Sail code for clarity based on jrtc27's suggestion.