* Add vector mask and reduction instructions

* Fix register overlap check in vector mask instructions

---------

Co-authored-by: xwan <xinlai.wan@rivai.ai>

* Add vector floating-point instructions

* Update vector floating-point conversion instructions

* Update copyright headers for vector extension code

---------

Co-authored-by: xwan <xinlai.wan@rivai.ai>

* Add vector arithmetic & mask instructions

* Update vector EEW and EMUL checking function

* Add vector instruction illegal check functions

* Adjust code formatting for vector instruction illegal check functions

Merge approved by team at tech-golden-model meeting on 2023-03-14.

* Add vector load / store instructions

* Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code

* Update vstart setting in vector load / store instructions

* Remove unnecessary assert statements in vector instructions

* Fix bugs in vleff instructions and revise coding styles

* Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure

* V extension general framework and configuration setting instructions

* Update model/riscv_insts_vext_utils.sail

fix a typo

Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Signed-off-by: BrighterW <xinlai.w@rioslab.org>

* Update model/riscv_insts_vext_vset.sail

* Revisions after Nov 22 meeting

* Update effect matching for functions in riscv_vlen.sail

* Fix code formatting issues

* Update model/riscv_insts_vext_utils.sail

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>

* Fix coding style issues

* Update vset instructions

Signed-off-by: BrighterW <xinlai.w@rioslab.org>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>
Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

Signed-off-by: Rafael Sene <rafael@riscv.org>

This may be more readable and also matches the sail-cheri-riscv model.
For now this keeps ~ overloaded to accept bool, but in the future we may
want to consider removing it (which is what I did to find all uses
modified in this patch)

This is useful for the sail-cheri-riscv model, where we would like to
reuse C_ILLEGAL, but can't right now since it is current defined too late.

It is needed for https://github.com/CTSRD-CHERI/sail-cheri-riscv/pull/69

Ubuntu 18.04 is being sunset.

Sail tries to check for pattern match completeness and issues warnings
but this often gives false positives: see discussion at
https://github.com/rems-project/sail/issues/191 .  To suppress these
we add a wildcard case that raises an internal error.  There is
effectively no behaviour change as these would previously have
resulted in a match error at runtime and they should be unreachable
anyway.

At the same time we change the DOUBLE case in memory access paths to
allow for xlen > 64.

Following discussion on the PR I also changed internal_error to take a
file and line number as an argument to aid with debugging.

Fixes: https://github.com/riscv/sail-riscv/issues/194

This can now be found in the Sail repository.
Includes an update to sail-riscv.install

Revert "added 3 new command line switches (plus functionality):  -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)" (#220)

Reverts #219. Merged without code review and with many issues.

This reverts commit 43b81eaf.

added 3 new command line switches (plus functionality):  -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)

* added 3 command-line switches:  -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond

* example commit

* fixed some type warnings/errors (between int/bool)

Previously the decoding hook (`ext_post_decode_hook`) allowed models to
override the decoded `ast`. However, this is not sufficient if model
extension changes interpretation of fields. Additionally, the assembly
printing would always print assembly for the "baseline decode" which
resulted in incorrect trace output in the sail-cheri-riscv model.

With the new hook models can implement ext_decode()/ext_decode_compressed()
to return an `ast` and for encodings that are not adjusted fall back to
the default `encdec`/`encdec_compressed`.

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

Signed-off-by: Jan Henrik Weinstock <jan@mwa.re>

This option causes handle_illegal to pass instbits as the value to set
for xtval, but instbits is never set so it ends up being 0 just as if
the option was never enabled. Fix this by initialising instbits during
fetch; we could make this conditional on whether the option is enabled
but that seems unnecessary and introduces tighter coupling.

Note that this option appears to have always been broken; when it was
originally added, instbits was only written two in two cases which were
both dead code and later removed in eb176111.

Closes: #173

After the last commit -fcommon is no longer required.

This reverts commit ffea7a39.

The sail C code generator will emit definions for these structs. The
duplicate definition linker error were worked around by adding -fcommon
in ffea7a39. This commit fixes the
underlying issue by declaring the variables as `extern`.

Merged after code review. Thanks everybody for helping.

* test: Ignore generated XML output

* run_tests: Build RVFI emulators too

Can't run tests with them though as they're built for direct instruction
injection (RVFI-DII) via an instruction stream over a network socket,
not fetching instructions from memory, so this remains just a build
test.

* run_tests/run_fp_tests: Print summary and give meaningful exit code

* run_tests/run_fp_tests: Include tests and failures in top-level XML entity

* run_tests/run_fp_tests: Use failure not error for XML output

The former is the standard tag for normal test failures, the latter is
for catastrophic things like test harness errors.

* Run ISA tests in CI

pull-requests ideally come with an explanation how the correctness of
the PR was established.

These are intended to deal with much of the low-hanging fruit; plenty of
room for improvement exists.

The order used for wildcard is not deterministic and varies between
systems. Sorting ensures the diffs are easy to inspect going forwards.

Closes: #142

NB: Smstateen support is missing in the model so enabling the Zfinx
extension provides an architectural covert channel via FCSR if
privileged software is not aware of Zfinx's existence.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

Co-authored-by: Ibrahim Abu Kharmeh <abukharmeh@gmail.com>