Make sure all memory access functions use 64-bit words

Manually unroll address translation. Probably not something we would
want to do, but shows that an automatic optimisation that can do this
would be useful

Make sure vector operations are set up correctly to be optimized by
the C backend, this fixes performance issues with the decode

Also copy ROOT file into the same directory

Reverts 7df2149e

Remove functions in prelude that are duplicates from those in Sail
library as this causes issues for the latex generation

. move prover files into a single support directory
. generated_models -> generated_definitions
. reset vector -> c_emulator

Moved the exmem effect from match_reservation to speculate_conditional;
Added a few comments.

Commit changes from rems-project/sail@b167a59affdb6428fa0656a092b335a3a6899d56 which was committed after forking sail-riscv from that repo. Adds some make targets for calling cgen WIP and interpreter.

Add build time COVERAGE option to build with gcc coverage. Attempt to choose amenable gcc and sail optimisation options in this case. Add a sed hack to remove very blank lines from sail c output for rvfi build.

Clean up flow-typing related operations in RISC-V prelude