- Jan 11, 2023
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Robert Norton authored
This adds command line arguments --boot-rom and --no-boot-rom to enable or disable the use of the boot ROM at the reset vector. The current behaviour (--boot-rom) initialises a small bit of memory at the reset vector to set up argument registers and then jump to the address specified by entry point of the ELF file. With --no-boot-rom the simulator just sets the initial PC to the entry point. For backwards compatibility the default is to use the boot-rom unless NO_BOOT_ROM is defined during compilation.
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- Nov 02, 2022
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Jessica Clarke authored
This option causes handle_illegal to pass instbits as the value to set for xtval, but instbits is never set so it ends up being 0 just as if the option was never enabled. Fix this by initialising instbits during fetch; we could make this conditional on whether the option is enabled but that seems unnecessary and introduces tighter coupling. Note that this option appears to have always been broken; when it was originally added, instbits was only written two in two cases which were both dead code and later removed in eb176111. Closes: #173
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- Aug 24, 2022
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Alex Richardson authored
After the last commit -fcommon is no longer required. This reverts commit ffea7a39.
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Alex Richardson authored
The sail C code generator will emit definions for these structs. The duplicate definition linker error were worked around by adding -fcommon in ffea7a39. This commit fixes the underlying issue by declaring the variables as `extern`.
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- Aug 09, 2022
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Brian Campbell authored
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- Jul 13, 2022
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Bilal Sakhawat authored
Merged after code review. Thanks everybody for helping.
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- Feb 16, 2022
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Jessica Clarke authored
* test: Ignore generated XML output * run_tests: Build RVFI emulators too Can't run tests with them though as they're built for direct instruction injection (RVFI-DII) via an instruction stream over a network socket, not fetching instructions from memory, so this remains just a build test. * run_tests/run_fp_tests: Print summary and give meaningful exit code * run_tests/run_fp_tests: Include tests and failures in top-level XML entity * run_tests/run_fp_tests: Use failure not error for XML output The former is the standard tag for normal test failures, the latter is for catastrophic things like test harness errors. * Run ISA tests in CI
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- Feb 03, 2022
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Martin Berger authored
pull-requests ideally come with an explanation how the correctness of the PR was established.
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- Jan 31, 2022
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Jessica Clarke authored
These are intended to deal with much of the low-hanging fruit; plenty of room for improvement exists.
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- Jan 21, 2022
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Bilal Sakhawat authored
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- Jan 20, 2022
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Bilal Sakhawat authored
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Bilal Sakhawat authored
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Bilal Sakhawat authored
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Jessica Clarke authored
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Jessica Clarke authored
The order used for wildcard is not deterministic and varies between systems. Sorting ensures the diffs are easy to inspect going forwards.
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Jessica Clarke authored
Closes: #142
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- Dec 05, 2021
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Bilal Sakhawat authored
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- Nov 23, 2021
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Jessica Clarke authored
NB: Smstateen support is missing in the model so enabling the Zfinx extension provides an architectural covert channel via FCSR if privileged software is not aware of Zfinx's existence. Co-authored-by:
Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by:
Ibrahim Abu Kharmeh <abukharmeh@gmail.com>
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- Nov 22, 2021
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Jessica Clarke authored
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- Nov 17, 2021
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Jessica Clarke authored
This reverts commit c5e62ea4.
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Ibrahim Abu Kharmeh authored
* Adds Zfinx enable flag * Hardwire misa.{f,d} and mstats.FS to 0 * Moving nan boxing functions to fdext_reg * Swaps register names for floating point instructions Adds new mapping to swap register names, and use it in all assembly clauses * Disable Floating point loads, stores and moves * Add X_or_F_s and X_or_F_d functions, and use them to access all registers for floating points Changes register accessed for floating point instructions and modify nan boxing functions for zfinx * Formatting Remove couple of misplaced whitespace, unnecessary parens * Fix inconsistent indentation in insts_dext file * Fix spacing in fdext_regs * Remove redundant comparasion with true/ false * Constistant tuples spacing and removes couple of unnecessary parens. * Consistent functions declaration & calls spacing and removes couple of unnecessary parens. * Consistent spacing and removes couple of unnecessary comparasion with true/false * Make spacing consistent * Remove checks from execution stage * Add checks to encdec stage
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- Nov 11, 2021
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Ben Marshall authored
Trying to make the behavior of aesks1i easier to understand, and more obviously correspond to the specification. - Ensure that the aes_decode_rcon function only accepts valid values, plus add comments. - Re-name operands to aesks1i rcon -> rnum to be in line with the specification - Re-structure the Sail code for clarity based on jrtc27's suggestion.
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Ben Marshall authored
Remove weird whitespace " );" -> ");" at end of expressions to be consistent with the rest of the code base. On branch scalar-crypto-tidy Changes to be committed: modified: model/riscv_insts_zkn.sail
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Ben Marshall authored
Add spaces pre/post used of "==" operator to be consistent with the rest of the code.
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- Nov 05, 2021
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Martin Berger authored
File is no longer needed, as per this discussion: https://github.com/riscv/sail-riscv/issues/119
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- Oct 26, 2021
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Jessica Clarke authored
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- Oct 23, 2021
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Brian Campbell authored
Fixes rems-project/sail#152
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- Oct 22, 2021
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Jessica Clarke authored
* Use bool for floating point comparison result Using bits_WU (bits(32)) or bits_LU (bits(64)) makes no sense, these are just boolean values, and having fixed-width types is a pain for suporting RV32D (since RV32D would need to truncate, but RV128D would need to extend). Instead represent these as an actual bool to match what the values really are. This could be done with bits(1) but the value is logically a boolean (like the built-in integer comparison operators) not a bit vector of length one so we convert to bool and back for a cleaner interface. * Support compiling RV32F with flen == 64 The code conflated flen and xlen; deconflating them and adding suitable assertions (rather than silently retiring as a no-op that doesn't bump instret) ensures that it can be compiled for RV32 with flen set to 64. Whilst here, add the extensions and truncations that would be needed for RV128F. Note that there are already suitable guards on the decode clauses to ensure these instructions are illegal on RV32. * Support compiling RV32D This copies various bits of XLEN generality from the F code. * Support RV32D loads/stores * Correctly initialise misa.D based on flen not xlen * Makefile: Enable D extension for RV32 This now works so can be enabled. * test: Enable RV32D tests
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- Oct 18, 2021
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Ben Marshall authored
Merged scalar-crypto pull request #99 of 1.0.0-rc2 spec work from Ben Marshall. See https://github.com/riscv/sail-riscv/pull/99.
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- Sep 09, 2021
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Jessica Clarke authored
Fix crash when fcsr.frm is invalid
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Jessica Clarke authored
Fix incorrect SV48_Vaddr bitfield
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- Aug 25, 2021
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Peter Sewell authored
tweak README for move to riscv organisation
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- Aug 22, 2021
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dylux authored
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- Aug 10, 2021
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Peter Rugg authored
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- Aug 03, 2021
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Robert Norton authored
Encourage use of `opam` and streamline by moving discussion of setting `SAIL_DIR` into a separate section about building using a custom Sail version.
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- Jul 29, 2021
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Robert Norton authored
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pes20 authored
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pes20 authored
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- Jul 28, 2021
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Thomas Bauereiss authored
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- Jul 27, 2021
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Brian Campbell authored
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