Add a temporary hack for corner cases involving address wrapping around. Pending a more reasoned solution this might allow continued TestRIG testing.

Add PCC checks to branches and jumps. Also switch to having PC register be absolute (even though architecturally it is relative to PCC.base). This makes it for easier alignment checks but we have to be careful when the PC becomes architecturally visible. Not sure which is better long term.

Fix bug in getCapBounds caused by difference in precedence of >> operator between riscv and cheri-mips preludes :-(

Add DDC translation to riscv memory instructions. Not an ideal factorisation because the DDC translation has to take place before alignment check and therefore can't happen in translateAddr. To be considered. Also fix a bug where registers where reversed in CapRegs vector and so DDC was getting cleared during initialisation!

Revert "Don't attempt to print asm of instruction for rvfi because I haven't implemented cheri assembly yet (revert when implemented)."
We now support assembly mappings.

This reverts commit d714f27b.

Don't attempt to print asm of instruction for rvfi because I haven't implemented cheri assembly yet (revert when implemented).

Add clearing of tags on memory writes (physical memory only for now). Remove apparently redundant MEMval etc. functions. Propagate wmvt effect in many places.

Use nextPCC instead of writing directly to PCC. Set TCCs to default on reset for backwards compatibility.

Use UEPCC, SEPCC and MEPCC instead of uepc, sepc and mepc. Take care that setting the offset might make the capability unrepresentable.

Implement most CHERI instructions except memory. Still need to implement exceptions and fetch behaviours.

Make a start on CHERI-RISCV -- just replace register file with capabilities and fix up prelude so that it type checks for now.