Commits · vasubu · github.com / riscv / riscv-v-spec

Nov 16, 2019
- Improve description of vasubu to reflect overflow can occur · ce5d1f68
  Andrew Waterman authored Nov 15, 2019
  
  ce5d1f68
- Fix formatting · c83a6bb6
  Andrew Waterman authored Nov 15, 2019
  
  c83a6bb6
- Removed scaled fixed-point multiply-add instructions. · 063b128b
  Krste Asanovic authored Nov 15, 2019
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Task group agreed that fixed scale amounts were of limited utility.
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  063b128b
- Changed vector AMOs to zero-extend addresses instead of sign-extend. · 86e62f63
  Krste Asanovic authored Nov 15, 2019
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Closes #330.
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  86e62f63
Nov 15, 2019
- Clarified encoding of vcompress. · da9ae369
  Krste Asanovic authored Nov 15, 2019
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Closes #252
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  da9ae369
- Clarified exception handling of widened scalar values. · b77e4933
  Krste Asanovic authored Nov 15, 2019
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Closes #323
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  b77e4933
- Added signed and unsigned versions of averaging add and subtract. · c2f3157e
  Krste Asanovic authored Nov 15, 2019
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Moved opcodes over to middle column in encoding table and dropped immediate forms.
Closes #256
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  c2f3157e
- Fixed incorrect 64 in table -> should be SEW bits in memory. · 7697fa2e
  Krste Asanovic authored Nov 15, 2019
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Closes #322
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  7697fa2e
- Had not updated opcode names in table. · 037edcf2
  Krste Asanovic authored Nov 15, 2019
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Closes #325.
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  037edcf2
Nov 13, 2019
- Fix bug in encoding table: vw[s]maccus.vv doesn't exist; vw[s]maccsu.vv does · 55f4b5d8
  Andrew Waterman authored Nov 12, 2019
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Fixes #324
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  55f4b5d8
Nov 11, 2019
- Clarified vcompress example. · 430ddd26
  Krste Asanovic authored Nov 11, 2019
  
  430ddd26
- Merge pull request #309 from xingmingjie/master · eed6e852
  Krste Asanovic authored Nov 11, 2019
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Fix typo.
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  eed6e852
- Merge pull request #317 from riscv/vmadc-optional-carry-in · 088d5497
  Krste Asanovic authored Nov 11, 2019
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Make carry-in optional for vmadc/vmsbc; re-encode vadc/vsbc accordingly
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  088d5497
- Merge pull request #321 from riscv/vslide-mask · f6f3d4bb
  Krste Asanovic authored Nov 11, 2019
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Clarify that vslide mask element indices correspond to dest, not source
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  f6f3d4bb
- Merge pull request #320 from riscv/vslide-vl · ee4d0995
  Krste Asanovic authored Nov 11, 2019
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vslideup writes up to vl-offset elts
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  ee4d0995
- Merge pull request #319 from riscv/sign-extend-slide · d06438e8
  Krste Asanovic authored Nov 11, 2019
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Sign-extend x[rs1] arguments to vslide1up/vslide1down
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  d06438e8
- Clarify that vslide mask element indices correspond to dest, not source · e510e9bf
  Andrew Waterman authored Nov 10, 2019
  
  e510e9bf
- vslideup writes up to vl-offset elts · bda81de3
  Andrew Waterman authored Nov 10, 2019
  
  bda81de3
- Sign-extend x[rs1] arguments to vslide1up/vslide1down · 52b28e59
  Andrew Waterman authored Nov 10, 2019
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This matches the extension behavior of vmv.s.x.
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  52b28e59
Nov 10, 2019
- Indexed load/stores now zero-extend vector of byte offsets instead of sign-extending. · 8d4492e9
  Krste Asanovic authored Nov 10, 2019
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Closes #303.
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  8d4492e9
- Clarified that "vector register group" includes LMUL=1 case. · 567dc715
  Krste Asanovic authored Nov 10, 2019
  
  567dc715
- Improved description of permute instructions. · c1d3b7f7
  Krste Asanovic authored Nov 10, 2019
  
  c1d3b7f7
Nov 05, 2019
- Make carry-in optional for vmadc/vmsbc; re-encode vadc/vsbc accordingly · 5a038da1
  Andrew Waterman authored Nov 04, 2019
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Resolves #316
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  5a038da1
Nov 04, 2019
- Fix description of vrgather.vx · 1c182dee
  Andrew Waterman authored Nov 03, 2019
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Closes #313
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  1c182dee
- vstart is not written on illegal-instruction exceptions · 5e5bed3e
  Andrew Waterman authored Nov 03, 2019
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This is arguably implied by the fact that vstart is only reset to 0
at the end of execution, but it's clearer to make it explicit.
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  5e5bed3e
- Fix typo · 28d1b817
  Andrew Waterman authored Nov 03, 2019
  
  28d1b817
Oct 29, 2019
- Fix typo in vfdot.vv (#311) · 13533f4a
  Kito Cheng authored Oct 28, 2019
  
  13533f4a
Oct 23, 2019

Fix typo. · a6e77263

xmj authored Oct 23, 2019

"four existing major opcodes" => "three existing major opcodes"

a6e77263

Oct 16, 2019
- Added roundoff function in description to clarify behavior of fixed-point rounding. · db4c6046
  Krste Asanovic authored Oct 15, 2019
  
  db4c6046
Oct 11, 2019
- Add psABI calling and syscall convention · 9381a5b6
  Andrew Waterman authored Oct 10, 2019
  
  9381a5b6
Oct 05, 2019
- Bumped date marker on spec after last TG meeting. · 55bb8f6f
  Krste Asanovic authored Oct 04, 2019
  
  55bb8f6f
- Changed assembler syntax to use w in operand suffix to distinguish... · 2712e29e
  Krste Asanovic authored Oct 04, 2019
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Changed assembler syntax to use w in operand suffix to distinguish double-width source vector register group.
Closes #246
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  2712e29e
- Removed widening left shifts. · 7946a289
  Krste Asanovic authored Oct 04, 2019
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Closes #289.
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  7946a289
Oct 04, 2019
- Fixed max vector length description. · 22929a63
  Krste Asanovic authored Oct 04, 2019
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Closes #204
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  22929a63
- Closes #285 · 30457444
  Krste Asanovic authored Oct 04, 2019
  
  30457444
- Merge branch 'master' of github.com:riscv/riscv-v-spec · 76466839
  Krste Asanovic authored Oct 04, 2019
  
  76466839
- Added vector widening left shifts. · 2d666cab
  Krste Asanovic authored Oct 04, 2019
  
  2d666cab
- Merge pull request #291 from riscv/vfncvt-rod · 5a3bb6d8
  Krste Asanovic authored Oct 04, 2019
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Add floating-point narrowing conversion with jamming
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  5a3bb6d8
Sep 29, 2019
- Merge pull request #297 from riscv/rounding-logic · 53a79940
  Krste Asanovic authored Sep 28, 2019
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Describe fixed-point rounding logic
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  53a79940
Sep 28, 2019
- Describe fixed-point rounding logic · bac9b213
  Andrew Waterman authored Sep 27, 2019
  
  bac9b213