Each specification can be in one of the following states:
Development
Stable
Frozen
Ratified

In order to avoid confusion around which specification version should be
implemented we add the current state as well as a description of that
state to the title page.

Signed-off-by: Stephano Cetola <scetola@linuxfoundation.org>

First release candidate for v1.0 for public review.

defining prestart, inactive, active, body, and tail sections, and
corrected discussion of what elements might be updated.
Closes #689.

Add space between VType's operands

Closes #687.

vm=0 encodings should be reserved for mask-logical instructions

Changed assembler mnemonic of unordered floating-point reductions `vfredsum` and `vfwredsum` to `vfredusum` and `vfwredusum` respectively.  Older names kept as aliases.
Closes #681.

Clarified that mask load and store instructions operate as if EEW=8, EMUL=1 with reduced vector length.
Closes #665.

Closes #652.

Allow mask-agnostic tails to be written with the value that would have been produced with a maximum vector length.
Closes #639.

Closes #640.

Closes #612.

Made clear that implementations can raise illegal instruction exceptions if EEW not supported for address offset in indexed vector memory instructions.
Closes #599

Closes #587.

Removed the "write 0" request for vtype.  Can only be written via  vsetvl and that definition gives correct behavior.
Closes #575.

Will be added as a separate vector extension at a later date but with a new encoding.
Closes #545.

and moved to standard extension section at end.

Closes #550.

Clarify that whole-register loads do use the encoded EEW

The old text points out that, because the in-memory layout and in-register
layouts are the same, the instructions behave the same as moving vectors
of bytes with EEW=8.  True enough as far as the data transfer, but not so
for the handling of evl/vstart: those actually do depend on the encoded EEW.

This choice is consistent with the later statement that "implementations are
allowed to raise a misaligned address exception on whole register loads",
meaning (a) that EEW is not truly a HINT and (b) the unit of transfer really
is elements, not bytes, even if the effect of a successful transfer is the
same.

Resolves #686

The value 0x1000 doesn't fit in 3 bits. I assume this is supposed to be 0 since the other formats use 1-6?

Resolves #679

Fix incorrect statement about vasub overflow

It's true that vasub can never overflow when rounding down or jamming,
but when rounding to nearest, overflow _can_ occur.

Resolves #659