For consistency with the unprivileged ISA spec, use the verb "depend"
to say that an extension requires and implies another.

Explicitly state the dependence between V and Zve*.

Correction to non-normative text. If EMUL < 1, segmented ld/st act as if it were 1 for purposes of determining the size of the destination register group.

Signed-off-by: Adrian Harris <48252020+aharris-ventana@users.noreply.github.com>

Signed-off-by: Adrian Harris <48252020+aharris-ventana@users.noreply.github.com>

Co-authored-by: Adam Latos <alatos@marvell.com>

Changed constraint on vsetvl to remain backwards-compatible.

Added vl setting constraint to avoid element groups being broken across strip-mine interations in vector-length-agnostic code.

Added comment on use of vmmv.m instruction with same source and destination to indicate register will be used as a mask.

According to 15.2, the `vcpop.m` instruction previously had the assembler mnemonic `vpopc.m` but was renamed to be consistent with the scalar instruction.

According to 15.1, `vmandnot` and `vmornot` have been changed to `vmandn` and `vmorn` to
be consistent with the equivalent scalar instructions.

v[f]slide1down respects the mask policy

Due to what appears to be an editing error in 9c83a017,
v[f]slide1down wasn't updated to respect the mask agnostic/undisturbed
policy for elt. vl-1.  It should.

h/t Brandon Wu

Vector instructions that process IEEE 754 binary16 numbers were included
in draft versions of the vector extension, but they were separated from
the V extension prior to ratification.  This PR adds them back.

The Zvfh extension adds IEEE 754 binary16 support to all FP instructions.

The Zvfhmin extension adds only the conversions to and from binary32.

This makes it easier to reference them.

* Clarify Zve* extensions

* "does not include" instead of "exclude"

* verb conjugation

While it is technically correct to use 2^(XLEN-1) here
and say 2^16 there, it invites confusion.

Eliminate conflicting interpretations or mathematical errors
by stating the exact limit of VLEN (and thus VLMAX).

Following up on 9a877e85,
add the note that Zvl* composes with V, and that Zve*
can compose with each other.

Some users have interpreted this spec to imply incompatibility between
Zve* and V (see e.g. https://reviews.llvm.org/D117854).

That's not the intent, and hopefully this patch clarifies that fact.

Follow-up to e0675aa7

Co-authored-by: lhtin-rivai <lehua.ding@rivai.ai>

Resolves #756

Make encodings reserved if the same vector register would be read with two or more different EEWs by the same instruction.

Moved discussion of illegal `vtype` values into section on configuration setting instructions, and expanded explanations.

Once ratified, we will provide nomenclature for the relationship
between vector extensions and Zfinx.  However, we'll need alternate
extension names: e.g., Zve32fx might correspond to Zfinx.

Resolves #741