This allows riscv-tests to be built with a compiler
that supports not just RVG.

These tests will likely never support non-standard big-endian systems.

Support multi configuration travis builds

it was unused and causing issues when building
with the linux toolchain

configure now respects the host flag, rather than hardcoding the risc-v
compiler

Two extra NaN test cases

I believe this is entirely within the RISC-V ISA spec:

 * fmv is defined to move IEEE floats
 * All otherwise-unspeficied floating-point operations canonicalize NaNs

This test fails on Spike, but passes on Rocket.  I believe this is the source
of my current torture failures.

The new RISC-V ISA spec mandates NAN bit patterns.  This test checks to make
sure that those bit patterns come out of fsqrt(-1).  These pass on both spike
and Rocket.

An additional _DWORD_RESULT version of the FP test macros is added to
facilitate floating-point tests that compare against particular bit patterns.

Add a top-level make clean target.

VM tests only support one core, so have the other cores hammer on the
memory system to attempt to catch simple coherence regressions.