Inform GCC that "sfence.vma" clobbers memory

I don't exactly understand why it has to be the way it is, but I just
want it to work.

Also fix a pylint complaint.

Debug: Usability Features

For one of the test addresses, use the highest possible one to ensure
that OpenOCD isn't secretly reading/writing more words than requested.

Instead, just give up on making the log files altogether now. Since
gdbserver.py makes its own log files it's not as necessary in any case.

This is yet another commit in an attempt to get the riscv-tools build to
actually fail if these tests fail.

Testing is a separate step.

Also fix Issue #64 by adding src_dir to the path to the targets file.

This would have prevented some bugs I committed earlier.

Also make sure vsim.log makes it into the generated log file.

rv64[ms]i-csr: Only emit F instructions when compiled for F.

Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.

Now it actually confirms that we're talking to two different cores which
have different values in their registers. Previously it could have been
fooled if eg. the thread command was a nop.

This is simpler and more reliable than playing around with lsof.
Specifically, it works if the OpenOCD command is "strace openocd" while
the previous code did not.

Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.

debug: Make the 'out of reset' tests apply reset

I'm using this for a target where misa is at an old address, to
set riscv use_compressed_breakpoints off

This shouldn't affect triggers set by the debugger, because running code
can't change those. When it does affect them, it breaks Hwbp1 which sets
the breakpoint before running the program.

At least in the test programs. There are other places where this causes
trouble as well.

Test gdb/OpenOCD during regular test run.

Move target definition into individual files.

Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.

Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.