This makes it easier to support tests with large memory footprints,
as the default 63 pages may be insufficient

Enable RNMIs if the extension is present, as the feature affects trap
behavior when RNMIs are masked.

Resolves https://github.com/riscv-software-src/riscv-tests/issues/460

Certain tests (particularly negative) may require a fault to occur.

However in order to pass the tests, page fault and traps must return back
to the tests. This patch add support for page fault and trap filtering
in env.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>

In "evict" function in v/vm.c, when evict a dirty page in user space, memcpy should be from that page, rather than to evicted page.

* update riscv_arch.h to support QEMU:
  add size attribute for tohost/fromhost
  add writing zero to (tohost + 4) to write_tohost

* revert the align of tohost/fromhost to 64 bytes

See also https://github.com/riscv/riscv-pk/pull/240

Minor clang-related fixes

The RISC-V Privileged ISA v1.10 uses stval instead of
sbadaddr. Although GCC can cope with sbadaddr, clang cannot. It fails
with:

  error: operand must be a valid system register name or an integer in
  the range [0, 4095]

The RISC-V Privileged ISA v1.10 uses satp instead of sptbr. Although
GCC can cope with sptbr, clang cannot. It fails with:

  error: operand must be a valid system register name or an integer in
  the range [0, 4095]

Modified the variable name in vm.c as well to ensure consistency and
avoid possible confusion.

Unconditionally clear mie register while disabling interrupts.

fix a building error

riscv64-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DENTROPY=0xf7930f7 -std=gnu99 -O2 -I/data/riscv/riscv-tools/riscv-tests/isa/../env/v -I/data/riscv/riscv-tools/riscv-tests/isa/macros/scalar -T/data/riscv/riscv-tools/riscv-tests/isa/../env/v/link.ld /data/riscv/riscv-tools/riscv-tests/isa/../env/v/entry.S /data/riscv/riscv-tools/riscv-tests/isa/../env/v/*.c rv32ui/simple.S -o rv32ui-v-simple
/opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `tohost':
(.tohost+0x0): multiple definition of `tohost'; /tmp/ccOTKaAa.o:(.sbss+0x10): first defined here
/opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `fromhost':
(.tohost+0x40): multiple definition of `fromhost'; /tmp/ccOTKaAa.o:(.sbss+0x8): first defined here
collect2: error: ld returned 1 exit status
/data/riscv/riscv-tools/riscv-tests/isa/Makefile:74: recipe for target 'rv32ui-v-simple' failed
make[1]: *** [rv32ui-v-simple] Error 1
make[1]: Leaving directory '/data/riscv/riscv-tools/riscv-tests/isa'
Makefile:28: recipe for target 'isa' failed
make: *** [isa] Error 2

Signed-off-by: Zhi Yong Wu <zhiyong.wu@sophgo.com>

Rvv 0.9

1. add rtz rounding instructions
2. add vfslide instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Don't make assumptions about delegatability in medeleg.

This isn't required for correctness, but it helps debugging (and, in a few
restricted scenarios, it avoids x-prop issues).

Closes #16

Ecall and vector

1. mstatus.vs is similar to mstatus.fs but desiged for vector extension.
2. add mstatus.vs initialization macro. The macro also enables floating unit.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Some simulators support semihosting feature to brigde syscall to host.
The change keep the exit syscall and the arguments in the related registers.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

This caused it to collapse to 0, preventing coherence_torture from doing
anything interesting at all...

Inform GCC that "sfence.vma" clobbers memory