Compilers are good at optimizing, and with functions it's abundantly
clear what all the types involved are. This change means we don't have
to be super careful about the type of values because of what the macro
might do to them that might cause overflow.

The only place where the return type matters is in printf-style
functions, and I made get_value32() for those cases where a change was
needed.

This should set the stage for simply copying the latest debug_defines.h
from the debug spec build again.

Change-Id: I5fb19d0cfc1e20137832a7b344b05db215ce00e1
Signed-off-by: Tim Newsome <tim@sifive.com>

target/riscv: Replace watchpoint value mask comparison value with macro.

This patch replaces ~(typeof(watchpoint->mask))0 with
WATCHPOINT_IGNORE_DATA_VALUE_MASK. This improves
readability and moves the RISCV target in line with
other targets.

Change-Id: I15ac4d4ee76098b304d9b22f720911ba4329c190
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>

Merge commit '05ee8891' from upstream

target/riscv: Stop caching writes to DPC

Conflicts:
	src/jtag/drivers/xds110.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg

Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28

target/riscv: gdb_regno_name takes an enum.

Otherwise it won't compile for me. Not sure why that doesn't affect the
automated builds.

Change-Id: Ic66c743e1698c4c0772e5601723cb5c711b4fa5c
Signed-off-by: Tim Newsome <tim@sifive.com>

target/riscv: Adding register tables to make register names consiste

From upstream

Since DPC is WARL (same rules as MEPC according to
the specification), it is possible that
writes to it won't result in the exact value present.
Therefore, writes to it shouldn't be cached, same as
with other WARL registers.

Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>

target/riscv: Fix memory access when MMU is enabled and address couldn't be translated

Added the ability to enter dimensionless registers

Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86
Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>

Remove mention of esp32c2, esp32c3 from doc

Remove mention of "riscv set_scratch_ram" from doc

target/riscv: Prevent dump_field() reading uninitialized memory

This command no longer exists, was removed in:
https://github.com/riscv/riscv-openocd/commit/ead2a595b8491ed48ce2ced81d2935dc8a4c4973



Remove it from the doc as well.

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

Targets "esp32c2" and "esp32c3" should not be mentioned in the doc
under "target types" because these are not standalone OpenOCD
targets.

They are merely a set of .cfg files which use the generic
"riscv" target.

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72
Signed-off-by: Tim Newsome <tim@sifive.com>

Removed deprecated gd32vf103_flash

Now:
1) If mmu is disabled, virt2phys succeeded and returns physical address
2) If mmu is enbaled, but translation fails, read/write_memory fails

Change-Id: I312309c660239014b3278cb77cadc5618de8e4de
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>

Removing flash driver "gd32vf103_flash".

This driver has been deprecated since June-1-2022, and was scheduled
for removal in June 2023.

Change-Id: Ib6f4dcba11e91a095b3a20eedd864589084b7fa9
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef

From upstream

Remove an extra call to kept_alive()

target/riscv: update debug register printers

Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>

This incorrect extra call has been removed in upstream code already
in March 2022, see https://review.openocd.org/c/openocd/+/6836

 .

Remove it from riscv-openocd as well.

Change-Id: Ie341f5578c8bfdc518adf1e4bc134919ab76f803
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

hgatp_mode in riscv_virt2phys_v defined by vsatp value

Change-Id: I20bd0356c63745423e23aec71f272fe2e32db88e
Signed-off-by: Tim Newsome <tim@sifive.com>

Conflicts:
	src/flash/nor/drivers.c
	src/target/riscv/riscv.c

Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd

Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"

Replace `vsatp` with `hgatp` (how it should be)

Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973

Merge down up to 0384fe5d from upstream.

contrib: Match upstream.

flash/stm32lx: Revert to upstream version.

Remove end-of-line whitespace.

Reintroduce checkpatch problem, because now we can handle them better.

Change-Id: Ib81b9910433ae1a240630b898edb19da8d2d5d83
Signed-off-by: Tim Newsome <tim@sifive.com>

Upstream has a checkpatch failure here. I had fixed it because I didn't
know how else to properly get around it back then. Reintroduce the
problem. Now this file is identical to upstream.

Change-Id: Ic03b6bb42945ddbcfd2fe12c0cab5b05eda1a50c
Signed-off-by: Tim Newsome <tim@sifive.com>