- Jun 13, 2017
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Palmer Dabbelt authored
When I disappeared the polls everywhere I forgot to sanitize the hartid after halting. This is an invariant that GDB expects: when you return from a halt whatever thread is marked as currently selected is the thread that the next register accesses reference.
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Palmer Dabbelt authored
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- Jun 08, 2017
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Megan Wachs authored
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- Jun 07, 2017
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Tim Newsome authored
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Tim Newsome authored
When gcc isn't optimizing well, it might not realize that it's not possible to return fd without initializing it, and then the build fails due to -Werror.
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- May 26, 2017
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Palmer Dabbelt authored
GDB seems to just go off the rails if I return a SIGINT.
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Palmer Dabbelt authored
I missed this event. It appears to do nothing.
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Palmer Dabbelt authored
This means I don't know what hart to look at, so I might as well invalidate the register cache. Without this, you might get stale registers the first time you ask for them.
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Palmer Dabbelt authored
I thought OpenOCD did this, but it looks like that doesn't happen when runningi in RTOS mode. With this I can get to the end of most of the RTOS tests, but they SIGINT instead of exiting.
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Megan Wachs authored
riscv-v11: Don't perform unexpected operation in cache_write
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- May 23, 2017
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Megan Wachs authored
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- May 16, 2017
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Palmer Dabbelt authored
This fixes a race condition when reading/writing memory.
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Palmer Dabbelt authored
The larger buffers are really slow on Spike.
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Palmer Dabbelt authored
This was just a sanity check.
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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Megan Wachs authored
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- May 12, 2017
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Palmer Dabbelt authored
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- May 10, 2017
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Palmer Dabbelt authored
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- May 06, 2017
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Megan Wachs authored
GDB might request registers even if target was not successfully initialized.
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Megan Wachs authored
Read from 0
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- May 02, 2017
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Megan Wachs authored
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Megan Wachs authored
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Megan Wachs authored
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- May 01, 2017
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Megan Wachs authored
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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- Apr 28, 2017
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Palmer Dabbelt authored
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- Apr 27, 2017
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Palmer Dabbelt authored
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Palmer Dabbelt authored
This is another thing that should be fixed correctly. Essentially this just uses the old codepath, which works for v0.11.
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Palmer Dabbelt authored
I'm not sure why this is necessary, but for some reason GDB is asking for registers before OpenOCD thinks there's been a halt. This is really just a workaround, but I need to refactor the v0.11 stuff anyway so I don't want to figure it out.
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Megan Wachs authored
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Megan Wachs authored
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Palmer Dabbelt authored
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This shouldn't have any meaningful effect on the v0.11 support, but it does add generic versions of many functions that will allow me to later refactor the v0.11 support so it's easier to maintain both ports. This started as an emergency feature branch and went on for a long time, so it's all been squashed down into one commit so there isn't a big set of broken commits lying around. The changes are: * You can pass "-rtos riscv" to the target in OpenOCD's configuration file, which enables multi-hart mode. This uses OpenOCD's RTOS support to control all the harts from the debug module using commands like "info threads" in GDB. This support is still expermental. * There is support for RV64I, but due to OpenOCD limitations we only support 32-bit physical addresses. I hope to remedy this by rebasing onto the latest OpenOCD release, which I've heard should fix this. * This matches the latest dra...
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- Apr 11, 2017
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Megan Wachs authored
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Megan Wachs authored
fespi: Reset may have occurred. Need to set TXWM again. There are probably more places that need this added.
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Megan Wachs authored
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- Apr 05, 2017
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Megan Wachs authored
Readmem autoexec
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Megan Wachs authored
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Megan Wachs authored
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