GDB might request registers even if target was not successfully initialized.

Read from 0

This is another thing that should be fixed correctly.  Essentially this
just uses the old codepath, which works for v0.11.

I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt.  This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.

This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest dra...

fespi: Reset may have occurred. Need to set TXWM again. There are probably more places that need this added.

Readmem autoexec

riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.

This reverts commit 466b7b48.

Read memory retry

riscv-v13: wait for idle in read_memory

read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.