This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.

Fix infinite loop in reset.

Share trigger code between 0.11 and 0.13 code.

The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.

Forgot to commit this follow up to PR #79

Use abstract command to access registers if possible

Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.

This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.

Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).

riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)

Disable debugger-set triggers on connect

Use LL for 64-bit defines, as Windows is LLP64

This should also fix bugs on ILP32 systems.

When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.

Add 32-bit build

Code taken from http://openocd.zylin.com/#/c/4178/

Fix 32-bit build errors.

Perform regular build with travis.

Add back support for type 1 triggers

Fix the multi-GDB mode bugs

Restore value of temporary register (s0) in examine OpenOCD procedure…

I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.

They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.

Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.

Also slightly improve debugging output.

I was just being lazy here.

Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart.  Those assertions
aren't sane very early in examine, so I avoid them.

Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.

This avoids a bunch of RTOS special cases.

Testsuite now passes on multicore target

Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.