This new version changes how we handle temporary registers: rather than
tracking them by hand (like in the old code), they're now tracked as
part of assembling programs.  The register save/restore assertion that
used to fire all the time no longer exists.

This assumes that v0.11 targets have one hart, and that v0.13 targets
have harts IDs that start at 0 and are concecutive.

This is a work in progress, but it's at the point where you can actually
debug multi-hart programs now.

Readmem autoexec

riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.

This reverts commit 466b7b48.

Read memory retry

riscv-v13: wait for idle in read_memory

read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.

Change-Id: I24d545cc259927301851fad446f812e95fd1c557