- Apr 07, 2017
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Palmer Dabbelt authored
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- Apr 06, 2017
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Palmer Dabbelt authored
This is a work in progress, but it's at the point where you can actually debug multi-hart programs now.
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- Mar 31, 2017
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Palmer Dabbelt authored
This reverts commit 647e1b78.
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Palmer Dabbelt authored
This reverts commit eb90a5e0.
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Palmer Dabbelt authored
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Palmer Dabbelt authored
riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
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Megan Wachs authored
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- Mar 25, 2017
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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- Mar 24, 2017
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Palmer Dabbelt authored
This reverts commit 466b7b48.
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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- Mar 23, 2017
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Palmer Dabbelt authored
Read memory retry
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Megan Wachs authored
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Megan Wachs authored
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Palmer Dabbelt authored
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- Mar 22, 2017
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Megan Wachs authored
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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Palmer Dabbelt authored
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Megan Wachs authored
riscv-v13: wait for idle in read_memory
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- Mar 16, 2017
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Megan Wachs authored
read_memory was doing autoexec-initialized commands, but wasn't using ac_busy_delay to add delay or wait between the commands. This isn't the optimal solution, but the whole read_memory sequence needs to be made more efficient anyway, so this was the quick and dirty solution.
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- Feb 28, 2017
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Tim Newsome authored
Change-Id: I24d545cc259927301851fad446f812e95fd1c557
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Tim Newsome authored
riscv: Ensure that hart is halted before attempting to examine it.
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Megan Wachs authored
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- Feb 26, 2017
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Tim Newsome authored
Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
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Tim Newsome authored
Replace the constants with the ones from the ISA spec, since those are not updated as often. Also delete a bunch of old code. Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
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Tim Newsome authored
Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
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- Feb 23, 2017
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Tim Newsome authored
The remote bitbang implementation is really slow when reading back data. During many operations, like writing a block of memory, we don't need to see the return data. By communicating this to the lower layers, we get huge speedups. Downloads to spike now are 295KB/s. That means the gdbserver.py download test now runs to completion, unfortunately it fails. Everything else is still passing, though, so I'm committing this change. Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
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- Feb 22, 2017
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Tim Newsome authored
To spike now we download at 5KB/s. But in real hardware performance should be pretty OK now. Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
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- Feb 21, 2017
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Tim Newsome authored
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
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Tim Newsome authored
Now 33/39 of the gdbserver tests pass! Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
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- Feb 18, 2017
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Tim Newsome authored
Not a great fix. There's still a problem with accessing 64-bit floating point registers on 32-bit cores. 24 of the gdbserver.py tests pass now. Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
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Tim Newsome authored
23 gdbserver.py tests pass now. Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
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Tim Newsome authored
Got rid of the last reference to the old debug RAM code! (Mostly?) SimpleF18Test passes now. Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
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- Feb 17, 2017
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Tim Newsome authored
This version was able to download code, and run to a breakpoint. Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
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- Feb 16, 2017
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Tim Newsome authored
The code doesn't do anything intelligent if errors are found. But MemTestBlock now also passes. I'm not quite sure why. Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
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Tim Newsome authored
Now passing MemTest{8,16,32,64} Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
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