This is just a placeholder; it may well change before standardization.

See https://github.com/riscv/riscv-v-spec/pull/351

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

1. vleb is read-only CSR to keep vector implementation lenght in byte
2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension
   state

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

See https://github.com/riscv/riscv-v-spec/commit/063b128bd91390c64796fe1e1546a8855fdbaf35

See https://github.com/riscv/riscv-v-spec/commit/da9ae36997183141521d3f850a935c99535ae73b

See https://github.com/riscv/riscv-v-spec/commit/c2f3157e34d3a0f77ccbbc502bdf1530da17aba8

See https://github.com/riscv/riscv-v-spec/pull/317

https://github.com/riscv/riscv-v-spec/pull/295

Closes #33

* (Partially) fix #30

With this change (and a renamed parse-opcodes) it's possible to as a
Python module without having to patch the repo.  Example:

  from parse_opcodes import parse_inputs

  if __name__ == "__main__":
      (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"])

* Fix #30: Rename parse-opcode to parse_opcode to enable module use

See https://github.com/riscv/riscv-v-spec/pull/247

See https://github.com/riscv/riscv-v-spec/pull/227

* rvv: fault-first also support segement

  based on 7.8.1, add missing segment supoort for fault first load

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvv: comparision instructions has 'm' prefix

  add 'm' prefix since the destination is mask register

  ref:
    https://github.com/riscv/riscv-v-spec/pull/181



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvv: reserved vid.v operand

  follow v0.7.1 change
  ref:
    https://github.com/riscv/riscv-v-spec/issues/160



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvv: add vfrsub.vf

  follow v-spec 0.7.1

  ref:
    https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* rvv: add amo encoding table

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Note that vmiota is being renamed to viota:
https://github.com/riscv/riscv-v-spec/pull/180