- Change AES32* and SM4* instructions back to regular R-type encoding.

 On branch scalar-crypto-v0.9.2
 Changes to be committed:
	modified:   opcodes-rv32k
	modified:   opcodes-rv64k
	modified:   opcodes-rvk
	modified:   parse_opcodes

vmv.x.s rd, vs2  dest should be rd

scalar-crypto: Add opcodes for RV32K, RV64K

Rvv v0.10

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Co-authored-by: Megan Wachs <megan@sifive.com>

- Adds opcodes for RV32 and RV64 scalar crypto.

- opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs

- opcodes-rv32/64k contains encodings which are for RV32 or RV64

- parse_opcodes has been modified:

  - Wnable instructions to be listed as either RV32 or RV64 only, allowing
    these opcodes to overlap.

  - The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or
    "DECLARE_RV64_ONLY" macros as needed.

  - The other backends have not been modified, and may need to be in the
    future.

 On branch scalar-crypto
 Changes to be committed:
	modified:   Makefile
	new file:   opcodes-rv32k
	new file:   opcodes-rv64k
	new file:   opcodes-rvk
	modified:   parse_opcodes

Remove the 'ok' value since this is redundant - an invalid instruction can
already be identified by a nil return value.

Also, include the script flags in the 'DO NOT EDIT' header.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

The Zbs v0.93 mnemonics unfortunately collided with Zbe.

Rvv pre 1.0 index and quad

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

See https://github.com/riscv/riscv-bitmanip/pull/89

See https://github.com/riscv/riscv-bitmanip/pull/88

Adding these four CSRs to parse_opcodes:
- 0x7a4 tinfo
- 0x7a5 tcontrol
- 0x7a8 mcontext
- 0x7aa scontext

The header explains where the file came from.

Rvv and hypervisor

This part copy the implementation which has been merged in spike

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

spike doesn't implement them but the disassembler use it

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

https://github.com/riscv/riscv-v-spec/commit/a67925038b653a75cd7eadb68b9915449941745d

https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5

https://github.com/riscv/riscv-v-spec/commit/cf03f382ab2e5cfa24874ebc7a190fb0311e3f9a

https://github.com/riscv/riscv-v-spec/commit/aa6032ce9ea4ef8c9f15e7dcb1fa6c7d7ac2d463