# Conflicts:
#	arch/riscv/kernel/setup.c
#	arch/riscv/kernel/smpboot.c

# Conflicts:
#	drivers/clk/sifive/Kconfig
#	drivers/clk/sifive/Makefile

# Conflicts:
#	arch/riscv/include/asm/perf_event.h

The ISA mandantes that stvec is 4-byte aligned, but we weren't actually
respecting this for .Lsecondary_park.  This trap vector is never
expected to actually be used unless there's a bug in early in the boot
process of the kernel, which explains why the bug wasn't noticed until
recently.

Thanks to Zong for finding the bug!

CC: zong@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

All RISC-V platforms today lack an IOMMU. However, legacy PCI devices sometimes
require DMA-memory to be in the low 32 bits. To make this work, we enable the
software-based bounce buffers from swiotlb. They only impose overhead when the
device in question cannot address the full 64-bit address space, so a perfect fit.

This patch assumes that DMA is coherent with the processor and the PCI bus. It
also assumes that the processor and devices share a common address space. This is
true for all RISC-V platforms so far.

This patch allows devices that require memory that can be addressed
using 32-bit addresses to work easily on RISC-V systems.  The newly
improved dma-direct ops will tap into this pool automatically for
32-bit addressing.

Based on an earlier patch from Wesley W. Terpstra.

CC: Wesley W. Terpstra <terpstra@sifive.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

Now that every user of MULTI_IRQ_HANDLER has been convereted over to use
GENERIC_IRQ_MULTI_HANDLER we can remove the references to
MULTI_IRQ_HANDLER.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

It appears that openrisc copied arm64's GENERIC_IRQ_MULTI_HANDLER code
(which came from arm).  I wanted to make this generic so I could use it
in the RISC-V port.  This patch converts the openrisc code to use the
generic version.

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

It appears arm64 copied arm's GENERIC_IRQ_MULTI_HANDLER code, but made
it unconditional.  I wanted to make this generic so it could be used by
the RISC-V port.  This patch converts the arm64 code to use the new
generic code, which simply consists of deleting the arm64 code and
setting MULTI_IRQ_HANDLER instead.

Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

This converts the ARM port to use the recently added
GENERIC_IRQ_MULTI_HANDLER, which is essentially just a copy of ARM's
existhing MULTI_IRQ_HANDLER.  The only changes are:

* handle_arch_irq is now defined in a generic C file instead of an
  arm-specific assembly file.
* handle_arch_irq is now marked as __ro_after_init.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

GENERIC_IRQ_MULTI_HANDLER is incompatible with MULTI_IRQ_HANDLER because
they define the same symbols.  Multiple generic irqchip drivers select
MULTI_IRQ_HANDLER, which is now defined on all architectures that
provide set_handle_irq().  This patch selects GENERIC_IRQ_MULTI_HANDLER
for all drivers that used to select MULTI_IRQ_HANDLER, but only when
MULTI_IRQ_HANDLER doesn't exist.  I'll then convert every architecture
over from MULTI_IRQ_HANDLER to GENERIC_IRQ_MULTI_HANDLER before removing
the extra MULTI_IRQ_HANDLER scaffolding.

CC: Shea Levy <shea@shealevy.com>
CC: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

This PCIe bridge only has a 32 bit bus master interface, thus truncating
the DMA capability of all PCIe devices attached beneath it. This caps
the child device capability so that these devices work on systems with
physical memory beyond the 4GiB threshold.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

There is currently no way for a PCIe bridge to impose constraints on
devices added to it.  For example, the Xilinx PCIe host bridge only
supports 32-bit physical addresses (due to a limitation on the AXI
port's address width).  Thus, even devices that claim to support 64-bit
DMA addresses must be restricted to 32-bit addresses when attached to
this host controller.

This patch adds a "add_dev" hook to pci_ops that allows the PCI
infastructure to interpose when adding a device, which in the case of
the Xilinx driver will be used to restrict the address ranges used for
DMA.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>