* pci/aw-reset-v5:
  PCI: Add pci_probe_reset_slot() and pci_probe_reset_bus()
  PCI: Remove aer_do_secondary_bus_reset()
  PCI: Tune secondary bus reset timing
  PCI: Wake-up devices before saving config space for reset
  PCI: Add pci_reset_slot() and pci_reset_bus()
  PCI: Split out pci_dev lock/unlock and save/restore
  PCI: Add slot reset option to pci_dev_reset()
  PCI: pciehp: Add reset_slot() method
  PCI: Add hotplug_slot_ops.reset_slot()
  PCI: Add pci_reset_bridge_secondary_bus()

Users of pci_reset_bus() and pci_reset_slot() need a way to probe
whether the bus or slot supports reset.  Add trivial helper functions
and export them as vfio-pci will make use of these.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

One PCI bus reset function to rule them all.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The PCI spec indicates that with stable power, reset needs to be
asserted for a minimum of 1ms (Trst).  We should be able to assume
stable power for a Hot Reset, but we add another millisecond as
a fudge factor to make sure the reset is seen on the bus for at least
a full 1ms.

After reset is de-asserted we must wait for devices to complete
initialization.  The specs refer to this as "recovery time" (Trhfa).
For PCI this is 2^25 clock cycles or 2^26 for PCI-X.  For minimum
bus speeds, both of those come to 1s.  PCIe "softens" this
requirement with the Configuration Request Retry Status (CRS)
completion status.  Theoretically we could use CRS to shorten the
wait time.  We don't make use of that here, using a fixed 1s delay
to allow devices to re-initialize.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Devices come out of reset in D0.  Restoring a device to a different
post-reset state takes more smarts than our simple config space
restore, which can leave devices in an inconsistent state.  For
example, if a device is reset in D3, but the restore doesn't
successfully return the device to D3, then the actual state of the
device and dev->current_state are contradictory.  Put everything
in D0 going into the reset, then we don't need to do anything
special on the way out.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Sometimes pci_reset_function() is not sufficient.  We have cases where
devices do not support any kind of reset, but there might be multiple
functions on the bus preventing pci_reset_function() from doing a
secondary bus reset.  We also have cases where a device will advertise
that it supports a PM reset, but really does nothing on D3hot->D0
(graphics cards are notorious for this).  These devices often also
have more than one function, so even blacklisting PM reset for them
wouldn't allow a secondary bus reset through pci_reset_function().

If a driver supports multiple devices it should have the ability to
induce a bus reset when it needs to.  This patch provides that ability
through pci_reset_slot() and pci_reset_bus().  It's the caller's
responsibility when using these interfaces to understand that all of
the devices in or below the slot (or on or below the bus) will be
reset and therefore should be under control of the caller.  PCI state
of all the affected devices is saved and restored around these resets,
but internal state of all of the affected devices is reset (which
should be the intention).

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Only cosmetic code changes to existing paths.  Expand the comment in
the new pci_dev_save_and_disable() function since there's a lot
hidden in that Command register write.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

If the hotplug controller provides a way to reset a slot, use that
before a direct parent bus reset.  Like the bus reset option, this is
only available when a single pci_dev occupies the slot.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

PCIe hotplug has a bus per slot, so we can just use a normal
secondary bus reset.  However, if a slot supports surprise removal,
a bus reset can be seen as a presence detection change triggering
a hot-remove followed by a hot-add.  Disable presence detection from
triggering an interrupt or being polled around the bus reset.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This optional callback allows hotplug controllers to perform slot
specific resets.  These may be necessary in cases where a normal
secondary bus reset can interact with controller logic and expose
spurious hotplugs.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

* pci/vipul-chelsio-reset-v2:
  PCI: Use pci_wait_for_pending_transaction() instead of for loop
  bnx2x: Use pci_wait_for_pending_transaction() instead of for loop
  PCI: Chelsio quirk: Enable Bus Master during Function-Level Reset
  PCI: Add pci_wait_for_pending_transaction()

New routine has been added to avoid duplication of code to wait for
pending PCI transactions to complete.  This makes use of that function.

Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

New routine has been added to avoid duplication of code to wait for
pending PCI transactions to complete.  This makes use of that routine.

Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Eilon Greenstein <eilong@broadcom.com>
Acked-by: David S. Miller <davem@davemloft.net>

T4 can wedge if there are DMAs in flight within the chip and Bus
Master has been disabled.  We need to have it on till the Function
Level Reset completes.  T4 can also suffer a Head Of Line blocking
problem if MSI-X interrupts are disabled before the FLR has completed.

Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

New routine to avoid duplication of code to wait for pending PCI
transactions to complete.

Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

* pci/misc:
  PCI: exynos: Split into Synopsys part and Exynos part
  PCI: mvebu: Make Marvell PCIe driver depend on OF
  PCI: mvebu: Convert to use devm_ioremap_resource

Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>

The Marvell PCIe host controller driver is heavily tied to Device Tree
APIs, and can only be used on platforms where the Device Tree is
used.  Therefore, it should "depends on OF" to avoid build failures on
!OF configurations.

Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Move the secondary bus reset code from pci_parent_bus_reset() into its own
function.  Export it as we'll later be calling it from hotplug controllers
and elsewhere.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

* pci/wei-resource-cleanups:
  PCI: Align bridge I/O windows as required by downstream devices & bridges
  PCI: Fix types in pbus_size_io()
  PCI: Add comments for pbus_size_mem() parameters
  PCI: Enumerate subordinate buses, not devices, in pci_bus_get_depth()

Commit 75096579

 ("lib: devres: Introduce devm_ioremap_resource()")
introduced devm_ioremap_resource() and deprecated the use of
devm_request_and_ioremap().

While at it, modify mvebu_pcie_map_registers() to propagate error code.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>

An upstream bridge's I/O window must be at least as aligned as any
downstream device or bridge requires.  In particular, if the upstream
bridge supports 1K alignment but a downstream bridge requires 4K alignment,
the upstream window must also be 4K aligned.

Therefore, do not reduce the required alignment ("min_align") based on
the upstream bridge's capabilities.

Reported-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Suggested-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This patch changes the type of "size" to resource_size_t and makes the
corresponding dev_printk() change.

[bhelgaas: changelog]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This patch fills in the missing description for two parameters of
pbus_size_mem().

Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Normally, on one PCI bus there would be more devices than bridges.  When
calculating the depth of a PCI bus, it would be more time efficient to
enumerating through the child buses instead of the child devices.

Also by doing so, the code seems more self explaining.  Previously, it went
through the devices and checked whether a bridge introduced a child bus or
not, which needs more background knowledge to understand it.

This patch calculates the depth by enumerating the bus hierarchy.

Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

* pci/misc:
  PCI: Fix comment typo for pci_add_cap_save_buffer()
  PCI: Return -ENOSYS for SR-IOV operations on non-SR-IOV devices
  PCI: Update NumVFs register when disabling SR-IOV
  x86/PCI: MMCONFIG: Check earlier for MMCONFIG region at address zero
  PCI: Convert class code to use dev_groups
  frv/PCI: Mark pcibios_fixup_bus() as non-init
  x86/pci/mrst: Cleanup checkpatch.pl warnings
  PCI: Rename "PCI Express support" kconfig title
  PCI: Fix comment typo in iov.c

* pci/aw-acs-fixes-v2:
  PCI: Claim ACS support for AMD southbridge devices
  PCI: Differentiate ACS controllable from enabled
  PCI: Check all ACS features for multifunction downstream ports

Fix trivial comment typo for pci_add_cap_save_buffer().

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Change the return value to -ENOSYS if a device is not an SR-IOV PF.
Previously we returned either -ENODEV or -EINVAL.

Also have pci_sriov_get_totalvfs() return 0 in the error case to make the
behaviour consistent whether CONFIG_PCI_IOV is enabled or not.

Signed-off-by: Stefan Assmann <sassmann@kpanic.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Currently, we only update NumVFs register during sriov_enable().
This register should also be updated during sriov_disable() and when
sriov_enable() fails.  Otherwise, we will get the stale "Number of VFs"
info from lspci.

[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

We can check for addr being zero earlier and thus avoid the mutex_unlock()
cleanup path.

[bhelgaas: drop warning printk]
Signed-off-by: ethan.zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>

AMD confirmed that peer-to-peer between these devices is
not possible.  We can therefore claim that they support a
subset of ACS.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Donald Dutile <ddutile@redhat.com>

We currently misinterpret that in order for an ACS feature to be
enabled it must be set in the control field.  In reality, this means
that the feature is not only enabled, but controllable.  Many of the
ACS capability bits are not required if the device behaves by default
in the way specified when both the capability and control bit are set
and does not support or allow the alternate mode.  We therefore need
to check the capabilities and mask out flags that are enabled but not
controllable.  Egress control seems to be the only flag which is
purely optional.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Donald Dutile <ddutile@redhat.com>

The multifunction ACS rules do not apply to downstream ports.  Those
should be tested regardless of whether they are single function or
multifunction.  The PCIe spec also fully specifies which PCIe types
are subject to the multifunction rules and excludes event collectors
and PCIe-to-PCI bridges entirely.  Document each rule to the section
of the PCIe spec and provide overall documentation of the function.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Donald Dutile <ddutile@redhat.com>

The dev_attrs field of struct class is going away soon, dev_groups
should be used instead.  This converts the PCI class code to use the
correct field.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

pcibios_fixup_bus() is called by pci_scan_child_bus(), which is not marked
__init.  Therefore, pcibios_fixup_bus() cannot be marked __init either.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This patch fixes warning and errors found by checkpatch.pl:

* replace asm/acpi.h, asm/io.h and asm/smp.h with linux/acpi.h,
linux/io.h and linux/smp.h respectively
* remove explicit initialization to 0 of a static global variable
* replace printk(KERN_INFO ...) with pr_info
* use tabs instead of spaces for indentation
* arrange comments so that they adhere to Documentation/CodingStyle

[bhelgaas: capitalize "PCI", "Langwell", "Lincroft" consistently]
Signed-off-by: Valentina Manea <valentina.manea.m@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>

The previous option title "PCI Express support" is confusing.  The name
seems to imply this option is required to get PCIe support, which is not
true.

Fix it to "PCI Express Port Bus support" which is more accurate.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

"Devic3" should be "device."

Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>