Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount"

This reverts commit be0555d5.

See #190

Add an api to get the name for a CSR.

See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7

- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked upon fetch

Fix the access exception during page-table walks to match the original access type, as specified in the manual. (#185)

It had been broken by 90bafe66.

Implement debug havereset bits

Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount

* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization.
Make state:reset() preserve misa.

* Set state.misa to max_isa on reset().

* Idiomatic fix for earlier commit.

This code is still a bit voodoo to me, but now we pass all the tests
again. (Stepping was broken by
4299874a.)

Add debug module authentication.

This allows the implementation of an alternative top-level simulator class.

The installed header files from the riscv subproject were incomplete, since
processor.h includes debug_rom_defines.h, and the latter was not installed.
Fix by moving it into riscv/, add it to the riscv subproject header list, which
ensures it will get installed.  While here, also add a missed dependency of debug_rom
on riscv/encoding.h to debug_rom/Makefile.

See https://github.com/riscv/riscv-isa-manual/pull/139

Not adopted yet, but I'm putting the implementation here for reference.

Add support for abstract debug access to CSRs and FPRs

Off by default, enabled with --debug-auth.
The protocol is very simple (definitely not secure) to allow debuggers
to test their authentication feature. To authenticate a debugger must:
1. Read authdata
2. Write to authdata the value that it just read, plus 1

I$ indices now maintain a 1:N relationship with PCs.  This is somewhat
faster and also simpler.

Add support for debug bus mastering

This lets the user control whether the system bus access implements bus
mastering.

* mem_t: Throw an error if zero-sized memory is requested

If for some reason the user requests a memory size of 0 megabytes, print
a useful error message.

* Check for overflow in memory size

If the user passes in a large enough memory size (-m) that the size in
bytes doesn't fit into size_t, catch this error in the make_mems function.

Add support for program buffer of size 2

Also add an implicit ebreak after the program buffer. This is not part
of the spec, but hopefully it will be.