For some reason, the old accessors for the non-sparse version were left
dangling.  These methods are used by the --kernel and --initrd options,
and so those options were just broken.

This also fixes a memory leak and refactors the implementation a bit.

Co-authored-by: Neel Gala <neelgala@incoresemi.com>

See https://github.com/riscv/riscv-isa-manual/issues/189#issuecomment-768525017

Brief:

- This commit adds spike support for the scalar cryptography extension.
  See the riscv-crypto repository (https://github.com/riscv/riscv-crypto)
  for more information on this extension.

- It is based on the experimental patch which has so far been kept in the
  riscv-crypto repository. Now that scalar crypto is nearly at the "freeze"
  stage and entering opcode consistency review, it makes sense to start
  upstreaming our experimental version.

- In terms of compiler support - we are using an experimental patch in
  the riscv-crypto repository at the moment, others are working on an
  upstream appropriate version.

Details:

- Add support for dedicated scalar crypto instructions.

- Add very basic support for the entropy source (entropy_source.h).
  Much of the behaviour of this is implementation specific. This model
  aims to provide the bare minimum of functionality which can be used to
  quickly develop software. It uses /dev/urandom as its entropy source for
  now.

- Scalar crypto is unique in that it _borrows_ instructions from the
  Bitmanipulation extension. This is currently _not_ encoded in the patch,
  as I didn't want to damage anything in Bitmanip which is currently under
  review. However, I've added a macro in riscv/decode.h called
  "require_either_extension(A,B)", which allows instructions to be valid
  opcodes iff they are in one or both extensions.

 On branch scalar-crypto
 Changes to be committed:
	modified:   README.md
	modified:   riscv/decode.h
	modified:   riscv/encoding.h
	new file:   riscv/entropy_source.h
	new file:   riscv/insns/aes64im.h
	new file:   riscv/insns/aes64ks1i.h
	new file:   riscv/insns/aes64ks2.h
	new file:   riscv/insns/aes_common.h
	new file:   riscv/insns/aesds.h
	new file:   riscv/insns/aesdsm.h
	new file:   riscv/insns/aeses.h
	new file:   riscv/insns/aesesm.h
	new file:   riscv/insns/sha256sig0.h
	new file:   riscv/insns/sha256sig1.h
	new file:   riscv/insns/sha256sum0.h
	new file:   riscv/insns/sha256sum1.h
	new file:   riscv/insns/sha512sig0.h
	new file:   riscv/insns/sha512sig0h.h
	new file:   riscv/insns/sha512sig0l.h
	new file:   riscv/insns/sha512sig1.h
	new file:   riscv/insns/sha512sig1h.h
	new file:   riscv/insns/sha512sig1l.h
	new file:   riscv/insns/sha512sum0.h
	new file:   riscv/insns/sha512sum0r.h
	new file:   riscv/insns/sha512sum1.h
	new file:   riscv/insns/sha512sum1r.h
	new file:   riscv/insns/sm3p0.h
	new file:   riscv/insns/sm3p1.h
	new file:   riscv/insns/sm4_common.h
	new file:   riscv/insns/sm4ed.h
	new file:   riscv/insns/sm4ks.h
	modified:   riscv/processor.cc
	modified:   riscv/processor.h
	modified:   riscv/riscv.mk.in

* files and collateral for adding spike as a target to the arch-test-framework

* minor typo fix

Co-authored-by: Neel Gala <neelgala@incoresemi.com>

This patch splites the target-requested memory regions into pages and only
allocates host memory when it is accessed to reduce larget memory sceniaro
in 64 bit target system

Co-authored-by: Dave.Wen <dave.wen@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Resolves #628

Resolves #625

Since we don't support RV128

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

See #617 for discussion.

Resolves #617.

Update config file to support aarch64

Check and use proc variable in MMU emulation

When deciding HS-mode interrupts in processor_t:take_interrupt()
we should use "~state.hideleg" instead of "~MIP_VS_MASK" because
VS interrupt bits are writeable in HIDELEG CSR.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We cannot blindly use proc variable in MMU emulation because external
debug emulation instantiates MMU with proc=NULL.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Misc fix 2020 12 14

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

When a single abstract command writes s0 and executes a program buffer
that leads to an exception, the value of s0 should still persist. The
fact that it did not masked the following bug in OpenOCD:
https://github.com/riscv/riscv-openocd/issues/559

Rvv fix 2020 12 04

ref:
  https://github.com/riscv/riscv-v-spec/commit/511d0b84a3848de437fd01990d078feaa2871b11



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Fix Issue #609 where extraneous debugging output was added when the user
invoked any simulation operation that involved addr_to_mem.

Add a core parameter to the interactive str command. This makes it
possible for the spike user to specify the device whose memory contains
the NUL-terminated string to be printed.