* SFENCE.VMA requires S-mode

* MSTATUS.SUM hardwired to 0 if no S-Mode

Closes #363

Partially reverts 0162a6e7

Closes #361

Add --priv command-line option to set which privilege modes are available

reset will copy max_isa over to state.misa.

rvv-0.8-2019-11

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

'require_vector' should appear in front of each instruction and this trigger
illegal exception when V extension isn't supported.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

remove unecessary checking

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

include
   1. unit-stride
   2. strided
   3. indexed
   4. fault-first

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

for most instruction which are in
    single, single, single/scalar/immediate format

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

include:
    1. integer comparison
    2. float comparison

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

include
   1. vredxxx
   2. vwredxxx

since reduction keep the accumulation result in pipeline and write 1 widen
element back to dst register.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

include
    1. narrow shift
    2. narrow clip
    3. wide mac

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

1. fix the ELAN check for vill
2. handle 'rs1 = x0'
3. make logic more readable

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

use 128bit to store temporary result to handle shift = 63 case in rv64

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

1. The rounding increment should be derived from the shift amount, not SEW.
2. Use 128bit to store temporary result to handle shift = 63 case in rv64

Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

* round-to-nearest-even: In the case that result[gb] = 0, the result
  should still be rounded up if result[gb-1] != 0 && result[gb-2:0] != 0
  (the usual round-to-nearest behavior outside of the tiebreaker).
* round-down: Since all uses of INT_ROUNDING() are immediately followed
  with a right shift by gb, clearing the lower bits is unnecessary.
* round-to-odd: The LSB should be OR'd only if result[gb-1:0] != 0.

Signed-off-by: Albert Ou <aou@eecs.berkeley.edu>

tail zero feature has been removed after v0.8-draft

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

don't use quiet api

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

has been removed in https://github.com/riscv/riscv-v-spec/pull/249



Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Implement support for big-endian hosts