- Jun 13, 2024
-
-
Andrew Waterman authored
This has no effect on Spike itself, but it might matter for anyone who's using Spike as a library in a multithreaded program.
-
- Jun 12, 2024
-
-
Andrew Waterman authored
Updated README with supported Vector Cryptography Extensions
-
Akif Ejaz authored
-
Andrew Waterman authored
Separate RV32 and RV64 C instructions into separate files
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
-
Andrew Waterman authored
We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N).
-
Andrew Waterman authored
- c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous
-
Andrew Waterman authored
-
Andrew Waterman authored
triggers: implement tcontrol
-
- Jun 11, 2024
-
-
YenHaoChen authored
Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0.
-
- Jun 01, 2024
-
-
Andrew Waterman authored
Avoid checking ELP before every instruction fetch
-
- May 31, 2024
-
-
Andrew Waterman authored
Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop.
-
Andrew Waterman authored
ELP will be zero if Zicfilp is not enabled.
-
- May 30, 2024
-
-
Akif Ejaz authored
-
akifejaz authored
-
Jerry Zhao authored
add support to load ET_DYN elf
-
- May 29, 2024
-
-
Clément Léger authored
When compiled as PIE, executable can be loaded at any memory address. Lately, OpenSBI switched to such behavior and spike was not able to load it anymore. This patch add an additional load_offset parameter for load_elf(). This load_offset value is passed as DRAM_BASE and used only for ET_DYN elfs. Signed-off-by:Clément Léger <cleger@rivosinc.com>
-
- May 28, 2024
-
-
akifejaz authored
-
- May 27, 2024
-
-
Andrew Waterman authored
Require vector extension when attempting vxsat writes
-
Andrew Waterman authored
vector: Not logging write of reduction instructions when vl = 0
-
Andrew Waterman authored
zicflip: fix [ms]ret behavior
-
- May 24, 2024
-
-
YenHaoChen authored
The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write.
-
- May 23, 2024
-
-
Chih-Min Chao authored
Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
-
- May 22, 2024
-
-
Andrew Waterman authored
Implement mcontrol6.hit
-
YenHaoChen authored
-
YenHaoChen authored
-
YenHaoChen authored
Avoid using private headers, e.g., debug_defines.h, in triggers.h
-
YenHaoChen authored
Add mcontrol_common_t::set_hit()
-
YenHaoChen authored
Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros
-
- May 21, 2024
-
-
YenHaoChen authored
-
- May 07, 2024
-
-
Andrew Waterman authored
Add Zawrs extension
-
Ved Shanbhogue authored
-
- May 03, 2024
-
-
Andrew Waterman authored
Zfa: fix: fmaxm.q requires Q instead of D extension
-