Commits · priv-1.10 · github.com / riscv / riscv-isa-sim

May 25, 2017
- minNum -> minimumNumber · 68c721b8
  Andrew Waterman authored May 25, 2017
  
  68c721b8
May 14, 2017
- Make C.LI/C.LUI trapping behavior match spec · e465de14
  Andrew Waterman authored May 13, 2017
  
  e465de14
May 06, 2017
- UXL=SXL=MXL · 12926c7a
  Andrew Waterman authored May 05, 2017
```
https://github.com/riscv/riscv-isa-manual/commit/326bec83de23f4d2daf24cfed6b5251748cad632
```
  12926c7a
- Trap superpage PTEs when PPN LSBs are set · 8a428c76
  Andrew Waterman authored May 05, 2017
  
  8a428c76
May 02, 2017
- Fix segfault when accessing bad memory addresses · 63c98b41
  Andrew Waterman authored May 01, 2017
  
  63c98b41
- Set default entry point from ELF · 75f2a05d
  Andrew Waterman authored May 01, 2017
  
  75f2a05d
May 01, 2017
- Add option to set start pc · 4859971a
  Andrew Waterman authored Apr 30, 2017
  
  4859971a
- Support more flexible main memory allocation · abb7dddf
  Andrew Waterman authored Apr 30, 2017
  
  abb7dddf
- Store both host & target address in soft TLB · 1d289240
  Andrew Waterman authored Apr 30, 2017
  
  1d289240
Apr 26, 2017
- FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X · 115297ef
  Andrew Waterman authored Apr 25, 2017
  
  115297ef
- Remove hret instruction · 9b6843b5
  Andrew Waterman authored Apr 25, 2017
  
  9b6843b5
Apr 11, 2017

Andrew Waterman authored Apr 10, 2017

https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ

d6fce459

Apr 08, 2017
- Implement vectored interrupt proposal · 5f494a22
  Andrew Waterman authored Apr 07, 2017
```
https://github.com/riscv/riscv-isa-manual/commit/4dcaa944ba40e074d25516a157fc37f7491b71cc
```
  5f494a22
Apr 06, 2017
- Add --enable-misaligned option for misaligned ld/st support · 1132fdf4
  Andrew Waterman authored Apr 05, 2017
```
Resolves #93
```
  1132fdf4
Apr 01, 2017
- update encoding.h to get PMP updates · f2e8eb28
  Yunsup Lee authored Mar 31, 2017
  
  f2e8eb28
- Update LICENSE copyright date · 32f8b0bb
  Andrew Waterman authored Mar 31, 2017
  
  32f8b0bb
Mar 30, 2017
- fdt: move interrupt controller into its own node · b04dfe31
  Wesley W. Terpstra authored Mar 30, 2017
  
  b04dfe31
Mar 28, 2017
- Set badaddr=0 on illegal instruction traps · 7b396b51
  Andrew Waterman authored Mar 27, 2017
  
  7b396b51
- On EBREAK, set badaddr to pc · 8f4fb411
  Andrew Waterman authored Mar 27, 2017
  
  8f4fb411
- Separate page faults from physical memory access exceptions · a80c695b
  Andrew Waterman authored Mar 27, 2017
  
  a80c695b
Mar 25, 2017
- Default to 2 GiB of memory · 1fa21741
  Andrew Waterman authored Mar 24, 2017
  
  1fa21741
Mar 24, 2017
- Require little-endian host · e83a0320
  Andrew Waterman authored Mar 23, 2017
  
  e83a0320
Mar 23, 2017
- riscv: replace rtc device with a real clint implementation · 46f1423c
  Wesley W. Terpstra authored Mar 22, 2017
  
  46f1423c
Mar 22, 2017
- sim: declare cores as interrupt-controllers for clint · 693fc45e
  Wesley W. Terpstra authored Mar 21, 2017
  
  693fc45e
- bootrom: set a0 to hartid and a1 to dtb before boot · 212d5198
  Wesley W. Terpstra authored Mar 21, 2017
  
  212d5198
- configstring: rename variables to dts · 0647cce5
  Wesley W. Terpstra authored Mar 21, 2017
  
  0647cce5
- riscv: remove dependency on num_cores · 4c80b12b
  Wesley W. Terpstra authored Mar 21, 2017
  
  4c80b12b
- bootrom: include compiled dtb · f7a75572
  Wesley W. Terpstra authored Mar 21, 2017
  
  f7a75572
- sim: create DTS instead of config string · 4198bc7c
  Wesley W. Terpstra authored Mar 03, 2017
  
  4198bc7c
- sim: define emulated CPU clock rate to be 1GHz · fcd0f3ab
  Wesley W. Terpstra authored Mar 03, 2017
  
  fcd0f3ab
- autoconf: put location of 'dtc' into config.h · c71db778
  Wesley W. Terpstra authored Mar 03, 2017
  
  c71db778
Mar 20, 2017
- PUM -> SUM; expose MXR to S-mode · ee80f285
  Andrew Waterman authored Mar 20, 2017
  
  ee80f285
Mar 17, 2017

Simplify interrupt-stack discipline · 5ed1c1f9

Andrew Waterman authored Mar 16, 2017

https://github.com/riscv/riscv-isa-manual/commit/f2ed45b1791bb602657adc2ea9ab5fc409c62542

5ed1c1f9

Mar 14, 2017
- Implement mstatus.TW, mstatus.TVM, and mstatus.TSR · 17e3ef96
  Andrew Waterman authored Mar 13, 2017
  
  17e3ef96
Mar 07, 2017
- Don't overload illegal instruction trap in interactive code · 3c8dafee
  Andrew Waterman authored Mar 07, 2017
  
  3c8dafee
Feb 27, 2017
- Sv57 and Sv64 are not spec'd yet · cbaa72d2
  Andrew Waterman authored Feb 26, 2017
  
  cbaa72d2
Feb 26, 2017
- New counter enable scheme · 6db07076
  Andrew Waterman authored Feb 25, 2017
```
https://github.com/riscv/riscv-isa-manual/issues/10
```
  6db07076
Feb 21, 2017
- serialize simulator on wfi · 13639b9c
  Andrew Waterman authored Feb 20, 2017
```
This improves simulator perf when a thread is idle, or waiting on HTIF.
```
  13639b9c
- Take M-mode interrupts over S-mode interrupts · b47e8c0a
  Andrew Waterman authored Feb 20, 2017
  
  b47e8c0a
- permit MMIO loads to MSIP bit · f478eef8
  Andrew Waterman authored Feb 20, 2017
  
  f478eef8