It's nearly free to do so, because it's just virtual address space.

@davidbiancolin recently fell into this pit when using context_t with VCS.

fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT

The opcodes were incorrect in riscv-opcodes; now they match the spec.

Add RV32E/RV64E base ISA support

h/t @jerinjoy

See #901

Requested by "LfX Security - Non Inclusive Language Alerts"

Refer to rvv-spec v1.0-rc2

Now it disassembles 0x0000 (invalid encoding of c.addi4spn) as c.unimp
(RVC).  Non-RVC variant of unimp pseudoinstruction (0xc0001073) is also
implemented.

Simplify float convert instructions

According the privileged spec, TSR is read-only 0 when S-mode is not supported. (https://github.com/riscv/riscv-isa-manual/blob/56515289e5999512fe578cdddf861b730d790018/src/machine.tex#L860-L861)

Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating
point) extension, consisting only of data transfer and conversion
instructions.

This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin"
as a multi-letter extension and adjusts feature gate for
data transfer / conversion instructions.

*   FLH / FSH
*   FMV.X.H / FMV.H.X
*   FCVT.S.H / FCVT.H.S
*   FCVT.D.H / FCVT.H.D (if 'D' extension is also present)
*   FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)

Simply floating point parameters and merge operations

Simplify narrowing instruction

Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX