Rvv pre 1.0

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

They aren't arch state

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

The original name misses the 'i' in instruction mae

vamoswape8  ->  vamoswapei8

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

The command parser still can accept SLEN but the value is not stored
in implementation

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

some dump and comparison tool may depennd the initial state of
vector register.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Incorporate RVV 1.0 vtype layout change

Some UCB implementations once used this to represent a pipeline bubble.
But this encoding is reserved for future standard HINT use.

Resolves #503

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

RISC-V H-Extension v0.6.1 Support

It is very inconvenient to always embed kernel flat image into
OpenSBI for booting Linux/Xvisor on Spike.

We add optional "--kernel" command line option for spike. Using
this new option, users can specify kernel flat image separately
and OpenSBI ELF separately.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We add bootargs command-line option to Spike which allows us to
provide custom kernel parameters to Linux and Xvisor.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We add new HFENCE, HLV, and HSV instructions for HS-mode which
are defined as part of the RISC-V hypervisor extension.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We extend our existing MMU implementation to support two-stage
translation when running VS-mode for RISC-V hypervisor extension.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We add newly defined hypervisor CSRs and allow M/HS-mode to access
these CSRs. The MRET, SRET, ECALL and WFI instructions have also
been updated so that virt-to-novirt switch and exception cause is
based on HART virtualization state.

Subsequent patches will implement two-stage page tables, HFENCE
instructions and HSV/HLV instructions.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

As section 3.6 says:
  The vstart CSR is defined to have only enough writable bits to hold
  the largest element index (one less than the maximum VLMAX) or lg2(VLEN) bits.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

With hypervisor extension, we have more CSRs providing trap
related information. We extend existing trap classes to pass
additional trap information required by hypervisor extension.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

We add missing CSR and instruction encoding related defines
for hypervisor extension.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

If n_pmp=0, then pmp is not implemented hence raise trap

Commitlog 2020 07 02

For csr register access instructions, there are log like

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Rvv fix 2020 06 25

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Rvv fix 2020 06 18

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>