It's 3 instructions shorter now.

* Update debug_defines from latest spec.

* Implement halt groups.

This lets the debugger halt multiple harts near simultaneously.

* Revert encoding, which I updated accidentally.

ee6fe650 didn't get this right,
as it failed to add the offset to the address when checking each
4-byte sector of the access against hte PMPs.

23 is the wrong line number. Avoid future problems by using a label.

openbsd port of spike and its build documentation

PMP checks should unconditionally fail if the PMP matches part of, but
not all of, an access.  We got this right, but went too far: we checked
whether _any_ PMP matches in this manner.  In fact, only the first PMP
that maches any of the bytes should be checked in this manner.

Add --dmi-rti and --abstract-rti to test OpenOCD.

This was a post-v1.10 amendment to the privileged spec.

https://github.com/riscv/riscv-isa-manual/commit/059f64c941856f249d8a0647e23e150dbdb1f62c

This prevents duplicate I/Os to buffered streams early in the program.

Optionally make spike behave more like real hardware, to automatically
test OpenOCD's handling of such hardware.

Now we do what the spec says we should do. This ended up not having any
effect on the current way OpenOCD performs system bus accesses.

Previously, the exception would only be raised if the store-conditional
would have succeeded.

Provide a noisy until interactive command

This is useful for example when the trace until a PC value needs
to be extracted (#246)

https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md

TODO: allow Spike users to override marchid/mvendorid/mimpid to
mimic their hardware implementations more closely.

Resolves #243

* Add "--log-cache-miss" option to generate a log of cache miss.

- This option must be used with "--ic" and/or "--dc" options
  to enable cache simulation.
- This option is useful with "-l" option to understand
  which instruction has caused the cache miss.

* Modify log format of cache miss to reduce log size.

Fix cut-and-paste bug in 64-bit SBA loads.

Fixes #234.

h/t Shane Lardinois

This fixes RVC disassembly.

It's done in a way that doesn't break 2cd60b27

This brings Spike into compliance with this clause in the spec:
https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96

1. When hitting a trigger during a single step, dcsr.cause must reflect
the trigger not the step.
2. Also check for triggers on accesses that require a slow path fetch.

h/t @taoliug

This fixes runtime crash when custom extension registers its
disassembly.