- May 30, 2024
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Akif Ejaz authored
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akifejaz authored
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Jerry Zhao authored
add support to load ET_DYN elf
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- May 29, 2024
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Clément Léger authored
When compiled as PIE, executable can be loaded at any memory address. Lately, OpenSBI switched to such behavior and spike was not able to load it anymore. This patch add an additional load_offset parameter for load_elf(). This load_offset value is passed as DRAM_BASE and used only for ET_DYN elfs. Signed-off-by:Clément Léger <cleger@rivosinc.com>
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- May 28, 2024
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akifejaz authored
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- May 27, 2024
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Andrew Waterman authored
Require vector extension when attempting vxsat writes
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Andrew Waterman authored
vector: Not logging write of reduction instructions when vl = 0
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Andrew Waterman authored
zicflip: fix [ms]ret behavior
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- May 24, 2024
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YenHaoChen authored
The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write.
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- May 23, 2024
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Chih-Min Chao authored
Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by:Chih-Min Chao <chihmin.chao@sifive.com>
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- May 22, 2024
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Andrew Waterman authored
Implement mcontrol6.hit
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
Avoid using private headers, e.g., debug_defines.h, in triggers.h
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YenHaoChen authored
Add mcontrol_common_t::set_hit()
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YenHaoChen authored
Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros
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- May 21, 2024
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YenHaoChen authored
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- May 07, 2024
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Andrew Waterman authored
Add Zawrs extension
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Ved Shanbhogue authored
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- May 03, 2024
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Andrew Waterman authored
Zfa: fix: fmaxm.q requires Q instead of D extension
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YenHaoChen authored
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- May 02, 2024
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Andrew Waterman authored
Remove old P extension
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Jerry Zhao authored
Support per-device arguments and device factory reuse
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- Apr 30, 2024
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LIU Yu authored
As proposed in #1652, we made the following changes to MMIO device (factory) plugin API, to mitigate current limitations and facilitate factory reuse. - removed `sargs` from `device_factory_t`, and introduced a new type alias `device_factory_sargs_t` to capture `<device_factory_t *, sargs>` pairs, this is used to instantiate sim_t instances; - changed the signature of `device_factory_t::generate_fdt` and `device_factory_t::parse_from_fdt` to take on an extra `sargs` argument, for instantiating devices with per-device arguments; - made `device_factory_t` const and potentially resuable across multiple `sim_t` instances.
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Andrew Waterman authored
Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
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Andrew Waterman authored
PLIC: Implement threshold masking
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Jerry Zhao authored
add hlvx pmp protect to fix issue 1557
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xinyuwang-sifive authored
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- Apr 29, 2024
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Andrew Waterman authored
Support Zicfiss (shadow stack access) with CFI extension v0.4.0
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- Apr 24, 2024
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Andrew Waterman authored
Make Zaamo + Zalrsc (Zba + Zbb + Zbs) imply A (B) in misa
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Andrew Waterman authored
Assert misa.B bit through --isa=...B...
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YenHaoChen authored
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YenHaoChen authored
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YenHaoChen authored
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- Apr 23, 2024
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YenHaoChen authored
The specification states that writes to read-only bits in a RW CSR are ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This PR proposes ignoring writes to read-only hstateen*[n] bits when mstateen*[n]=0 instead of writing the bits to 0.
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