1. Oct 14, 2021
  2. Oct 06, 2021
    • Andrew Waterman's avatar
      Fix editing error in mtval/stval definition · 399c9a75
      Andrew Waterman authored
      Partially introduced by 7f45777b and 94ab414c4b470edae8bde4e7759163fe7ddf8ab4
      
      The spec says that the platform will define which exceptions must populate
      mtval or stval with a nonzero value and which are permitted to zero it.
      But then later statements seem not to permit the possibility of zeroing
      the register, which is a contradiction.  Resolve in a backwards-compatible
      manner by permitting zeros unless the platform says otherwise (which was
      the original intent, anyway).
      
      This permits e.g. zeroing mtval on an EBREAK instruction, where mepc
      provides sufficient information, as was the intent of 94ab414c4b470edae8bde4e7759163fe7ddf8ab4.
      399c9a75
  3. Oct 05, 2021
  4. Oct 02, 2021
  5. Sep 30, 2021
    • Andrew Waterman's avatar
      Improve description of FENCE.TSO · e511c466
      Andrew Waterman authored
      The description of FENCE.TSO as "optional" was incorrect.  It has always
      been a mandatory instruction (because of the requirement that unused
      patterns in the fm field be treated as though fm=0).
      e511c466
  6. Sep 22, 2021
  7. Sep 16, 2021
  8. Sep 15, 2021
  9. Sep 11, 2021
  10. Sep 10, 2021
    • Andrew Waterman's avatar
      Generalize SSIP to support forthcoming interrupt controllers (#726) · 01069ac9
      Andrew Waterman authored
      * Changes to SSIP to support forthcoming interrupt controllers
      
      * Re: SSIP, say more by saying less
      01069ac9
    • Andrew Waterman's avatar
      Speculative implicit reads, v2 (#724) · bac0a5d0
      Andrew Waterman authored
      * Speculative implicit reads, v2
      
      These constraints are better expressed as PMAs, and so we relax the
      unprivileged spec to always allow speculative implicit reads "unless
      otherwise specified", then move the constraints into the PMAs.
      
      This proposal piggybacks on the non-idempotence PMA, constraining implicit
      reads to within a power-of-2 region of a non-speculative implicit read.
      Furthermore, speculative instruction fetch can also access the subsequent
      power-of-2 region.
      
      * Add preface entry
      bac0a5d0
    • Daniel Lustig's avatar
      Fix a typo in Figure A.13. (#733) · 216aa2b9
      Daniel Lustig authored
      Thanks to @YenHaoChen.
      
      Closes #731
      216aa2b9
  11. Sep 09, 2021
  12. Sep 06, 2021
    • John Hauser's avatar
      Make virtual instruction exceptions more consistent for VU mode (#730) · 0abcad44
      John Hauser authored
      Raise a virtual instruction exception when V = 1 if an attempted 
      instruction is HS-qualified but is explicitly blocked by either a 
      hypervisor CSR or a supervisor CSR.  Previously, the document was 
      inconsistent whether an illegal instruction or virtual instruction
      exception is raised when an instruction is blocked from executing in
      VU mode solely by a supervisor CSR such as scounteren.
      0abcad44
  13. Sep 03, 2021
  14. Sep 02, 2021
  15. Aug 31, 2021
  16. Aug 30, 2021
  17. Aug 29, 2021
    • Andrew Waterman's avatar
      Add mconfigptr CSR (#697) · 25b1abef
      Andrew Waterman authored
      * Add Smdisc extension (i.e. mconfigptr CSR)
      
      * mconfigptr may be hardwired to zero
      
      * Add changelog entry for mconfigptr
      
      * Fix mconfigptr preface entry
      
      "points to the address of" implies an extra level of indirection.
      Should be "points to" or "contains the address of"
      25b1abef
    • John Hauser's avatar
      Replace "EEI" with "execution environment" (#723) · 8551bd20
      John Hauser authored
      Make the manual more correct and consistent by dropping the term
      _execution environment interface_ and its abbreviation _EEI_ and
      replacing them everywhere with just _execution environment_.
      8551bd20