This might be a bit pedantic, but the current wording in the spec mixes
up traps and execptions here in a way that makes it sound like
interrupts don't write {m,s}epc if you're reading quickly.

I don't really like the wording I've proposed, so this is more of a bug
report than a fix.

interrupts wrt execution environment.

be considered non-standard, but could be future standard variants.

are considered globally enabled for privilege modes greater than the
current mode regardless of the setting of the global interrupt enable
for the higher privilege mode.

Addresses #145

Closed #73.

* Help the reader by pointing at TVM and TW in the relevant sections

* Mention TSR field in SRET description

* Avoid leaking M-mode details in S-mode text.

* Added a ref in SFENCE.VMA paragraph (PMP synchronization)

Commit b124462c

: (Remove SBI chapter) removed sbi spec
from privileged spec. But the sbi.tex never got removed
from. The plan was to maintain the sbi spec as a separate
repo.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

- The note about RCpc/RCsc in the literature is commentary, not
normative.

- Add a new note to make it a little more obvious that syntactic
dependencies can originate from SC instructions too.

Thanks to Ken Dockser again.

Changes to intro as part of rationalizing ISA into ISA-only versus platform-mandates,  and to make clearer there can be alternative privileged architectures.

Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual into tymcauley-misc-fixes

Also, clarify that they should be considered commentary.

The notes about PPO rules becoming redundant are really commentary.
The note about code assuming Ztso is not just commentary; it is
actually a requirement imposed by the extension.

when V = 1 to VS-mode and VU-mode.

Clarify that AMOs are always stores, and clarify fence.tso configs