Luc had provided the correct figure originally, but I must have messed
something up in the merge upstream.  This restores the correct figure.

This won't ever happen if medeleg[9] is hardwired to 0, but medeleg[9]
isn't required to be hardwired to 0.

for mtvec, and clarified that different modes can have different
mtvec alignment constraints.

The paragraph of text describing C.ADDI4SPN states the instruction is
RV32C/RV64C-only, but the opcode map indicates the instruction is
available for RV128C too.  This change updates the descriptive text,
assuming that the opcode map is correct.

(They're reserved for future use)

  required to, clear LR reservations if A extension present.

Added comment that we might consider different pattern for RV128 to improve compatibility with RV64.

The commit 3f05dd6e from 2018-06-02 lost a closing brace.
This patch restores it.