Other WARL registers seem to be explicit (e.g. "The misa CSR is a WARL
read-write register..."). This patch adds a similar indication for
mtvec. This consistency is important, as otherwise the reader will spend
time trying to determine if the behaviour is different. You can
determine it's WARL by reading the field layout diagram, but I think a
little redundancy in favour of easing readability makes sense.

At least one simulator started off trapping on invalid field
modifications
<https://lists.gnu.org/archive/html/qemu-devel/2018-04/msg04510.html>.

Closes #389

The commentary indicates that sharing mcycle between harts is mandatory,
but I don't think that's a good idea -- both because it's introducing a
constraint that is very hard to formalize (ie, WTF is a core) and
because I think some systems will desire different behavior.

This patch softens the wording in the commentary to avoid the appearance
that sharing mcycle between threads is mandatory.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

When reading through the manual for the QEMU patches to implement
mcounterinhibit I found that the commentary allows mcycle to be shared
between harts.  I actually really don't like this behavior, but I can
understand that it may make sense for some systems.  Regardless, the
normative text of the ISA manual should match the commentary.

This patch introduces the concept that modifications of a CSR on one
hart may cause the value on other harts to change.  If I understand
correctly that's not quite a WARL field, which can only change upon
writes.  I don't think it's worth giving this a name, though, as
hopefull it'll only apply to mcycle.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

cc @fintelia

Closes #399

Changes to unprivileged spec for bi[g]-endian support

Closes #375

Add endianness control proposal to priv spec

Contributed by @jhauser-us

Courtesy @jhauser-us