The non-normative text erroneously suggested that only accesses to
time/cycle/mcycle need be ordered by FENCEs.  In fact, other CSR accesses are
also visible to other harts, including interrupt-pending CSRs.

(The preceding normative text has no such deficiency.)

* Make explicit the priorities of synch. exceptions of H extension

* "page guest-fault" -> "guest-page fault"

1. For RV32, mstatush is now always required to exist.
2. mstatus.MPP is not just one bit.

This approach is more extensible, and now implicitly includes
writes to sstatus.SIE / mstatus.MIE, as it should.

As stated clearly by the preceding text, the baroque sequence for updating
mtimecmp is for RV32.  RV64 simply uses aligned loads and stores.

Closes #639

Closes #534

One, clarify the rules for virtual instruction exceptions by adding the
concept of _HS-qualified_; and two, make a special case for accesses to
32-bit high-half CSRs like cycleh and htimedeltah.  Also, when WFI is
attempted in VU mode, the exception depends on mstatus.TW.

If any addresses are invalid, mepc must be able to hold at least one of them.

Supersedes #590

See new non-normative text for explanation

Reordered sections to remove forward references.

Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>