Resolves #239

* Clarify interrupt delegation semantics

* Update contributors

* Some edits and fixes to memory model sections.

* Also fix a typo spotted by @daniellustig.

Closed #224.

* Add Ariane to marchid

* Add RI5CY to marchid.md

Add BOOM.

* Fix broken link

* Add marchid document

Closed #215

Luc had provided the correct figure originally, but I must have messed
something up in the merge upstream.  This restores the correct figure.

This won't ever happen if medeleg[9] is hardwired to 0, but medeleg[9]
isn't required to be hardwired to 0.

for mtvec, and clarified that different modes can have different
mtvec alignment constraints.

The paragraph of text describing C.ADDI4SPN states the instruction is
RV32C/RV64C-only, but the opcode map indicates the instruction is
available for RV128C too.  This change updates the descriptive text,
assuming that the opcode map is correct.

(They're reserved for future use)