Update the GH Actions that builds the Asciidoc branch

Signed-off-by: Rafael Sene <rafael@riscv.org>

Fix asciidoc build within the build directory

Adding back the missing text and anchors.

Fixing anchors that didn't convert and register diagrams that didn't
convert.

Table formatting and cleanup.

Reformatted table to asciidoc and added in missing words.

Cleaned up table to asciidoc formatting.

Reformatted table.

Formatted the debug module status table.

Trying to get the build to look in the correct directories.

Change back to what I had before.

Setting target for make.

Updated verify to fix github build.

Add --adoc to registers.py.

Reformatted table. Added in missing words and anchors.

Looks OK.

Still missing:
* pretty register pictures
* macros for each register and field that automatically format
  consistently and link to the register/field definition

Usage: `registers.py --adoc <XML file>`

Set %autowidth on table.

Removed %autowidth and set column widths to 1 & 3 respectively.

Fixing the access memory table, adding back missing words and
adding anchors.

Added access command diagrams and some conversion cleanup.

Formatting tables.
Adding in bytefield and wavedrom diagrams.

Removing duplicate words chapter and section.

When referencing a section or chapter with asciidoc, the words section
and chapter are inserted automatically, therefore no need to explicitly
type them.

Fixing github verify build.

COnversion cleanup

Cleaning up tables.

Fixing tables and text

Added abstract_commands.adoc to git tracking.

Converted abstract_commands to adoc file and added it as an
include in debug_module adoc file.

Adding in missing words and cleaning up tables.

Adding in missing words and general conversion cleanup.

Added back in missing words that didn't convert.

Adding back all of the missing words that didn't convert correctly and
cleaning up conversion issues.

* Clarify matching on invalid virtual addresses behavior

See:
* https://lists.riscv.org/g/tech-debug/message/1407
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Notes.pdf
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Slides.pdf

* Allow invalid addresses not to match at all.

Also clarify tdata2 requirements for triggers that are only used for
address matches.

tools: Remove unnecessary parens.