Commits · qa_csr · github.com / riscv / riscv-debug-spec

May 01, 2018
- QA CSR Example: save to arg0 not arg2 · c6e92dbd
  Megan Wachs authored Apr 30, 2018
  
  c6e92dbd
- Correct tense in QA CSR example · bda319d8
  Megan Wachs authored Apr 30, 2018
  
  bda319d8
- Examples: Give an example of CSR access with Quick Access · 65458c25
  Megan Wachs authored Apr 30, 2018
  
  65458c25
- Overview Diagram: increase number of Progbuf words (#267) · 848cca1a
  Megan Wachs authored Apr 30, 2018
```
* Overview Diagram: increase number of Progbuf words

* Conver dia to eps/pdf
```
  848cca1a
Apr 25, 2018
- fix misspelled name · a719ee6e
  Megan Wachs authored Apr 25, 2018
  
  a719ee6e
Apr 24, 2018
- Merge pull request #259 from riscv/clarify_triggers · e752307d
  Tim Newsome authored Apr 23, 2018
```
Clarify triggers
```
  e752307d
- Fix typo. · 097c701a
  Tim Newsome authored Apr 23, 2018
  
  097c701a
- Incorporate review feedback. · 01dabd5f
  Tim Newsome authored Apr 23, 2018
  
  01dabd5f
Apr 19, 2018
- Add trigger examples for match types 1, 4, and 5 · ca7a9d01
  Tim Newsome authored Apr 18, 2018
  
  ca7a9d01
- Give a few trigger examples. · cd5a15c6
  Tim Newsome authored Apr 16, 2018
  
  cd5a15c6
- Clarify that maskmax applies only to NAPOT trigger · 4375927f
  Tim Newsome authored Apr 12, 2018
  
  4375927f
Apr 18, 2018
- Merge pull request #230 from riscv/future · 93d5ca8b
  Tim Newsome authored Apr 17, 2018
```
Remove implemented features from Future Ideas.
```
  93d5ca8b
- Merge branch 'master' into future · 865b6eef
  Tim Newsome authored Apr 17, 2018
  
  865b6eef
Apr 17, 2018
- Merge pull request #256 from riscv/nmi_clarification · 94b371a2
  Megan Wachs authored Apr 16, 2018
```
NMI Clarification
```
  94b371a2
- Merge branch 'master' into future · 00e2698e
  Tim Newsome authored Apr 16, 2018
  
  00e2698e
Apr 14, 2018
- Merge pull request #254 from riscv/sba_errors · 2baf36b4
  Tim Newsome authored Apr 13, 2018
```
Clarify SBA unsupport access size error.
```
  2baf36b4
- NMI: debugging may not be possible if an NMI happens · acadfe9c
  Megan Wachs authored Apr 13, 2018
  
  acadfe9c
Apr 13, 2018
- Another attempt at SBA errors. · 8fb190c5
  Tim Newsome authored Apr 12, 2018
  
  8fb190c5
Apr 12, 2018
- Core Debug: all interrupts are masked includes NMI · 714c5d1b
  Megan Wachs authored Apr 11, 2018
  
  714c5d1b
- DCSR: add nmip bit to indicate NMI is pending · 56fbd9d6
  Megan Wachs authored Apr 11, 2018
  
  56fbd9d6
Apr 11, 2018
- Clarify SBA unsupport access size error. · fffe3c2a
  Tim Newsome authored Apr 10, 2018
```
Maybe solves #252.
```
  fffe3c2a
- Merge pull request #253 from riscv/sbdata · 5db6dad4
  Tim Newsome authored Apr 10, 2018
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Clarify high bits of sbdata in narrow reads.
```
  5db6dad4
- Clarify high bits of sbdata in narrow reads. · b4006ac7
  Tim Newsome authored Apr 10, 2018
  
  b4006ac7
Mar 31, 2018
- Merge pull request #249 from riscv/progbuf · 8cf7794d
  Tim Newsome authored Mar 30, 2018
```
Explain why progbufsize=1 is special
```
  8cf7794d
Mar 29, 2018
- Clarify progbuf=1 some more · 4ca83dd3
  Tim Newsome authored Mar 28, 2018
  
  4ca83dd3
Mar 28, 2018
- Merge pull request #235 from riscv/window · 8dd94e2f
  Tim Newsome authored Mar 27, 2018
```
hawindowsel can be smaller, depends on # of harts
```
  8dd94e2f
Mar 27, 2018
- Clarify debugger requirements when progbufsize=1 · 3b622438
  Tim Newsome authored Mar 26, 2018
  
  3b622438
- Explain why progbufsize=1 is special · ffba4d09
  Tim Newsome authored Mar 26, 2018
  
  ffba4d09
Mar 23, 2018
- Merge pull request #245 from riscv/haltsum · db9bc04b
  Tim Newsome authored Mar 22, 2018
```
Nonexistent/unavailable harts are not halted.
```
  db9bc04b
- Merge branch 'master' into haltsum · a3732722
  Tim Newsome authored Mar 22, 2018
  
  a3732722
Mar 21, 2018
- Merge pull request #236 from riscv/cmderr · 4e7da726
  Tim Newsome authored Mar 20, 2018
```
Clarify abstract command errors.
```
  4e7da726
- Merge branch 'master' into cmderr · 3279a70b
  Tim Newsome authored Mar 20, 2018
  
  3279a70b
- Merge pull request #247 from riscv/correct_haltsum1 · b51c59b9
  Megan Wachs authored Mar 20, 2018
```
haltsum1: correct its address 
```
  b51c59b9
- Merge pull request #225 from riscv/chisel_travis · c0e8dd3e
  Megan Wachs authored Mar 20, 2018
```
travis: add 'make chisel' target to regression
```
  c0e8dd3e
Mar 20, 2018
- haltsum1: correct its address to be BWC and not overlap with ABSTRACTAUTO · 6b88905d
  Megan Wachs authored Mar 19, 2018
  
  6b88905d
- Correct some inaccuarices in the chisel generated files · 2382e2e9
  Megan Wachs authored Mar 06, 2018
  
  2382e2e9
- travis: add 'make chisel' target to regression · 3e88e113
  Megan Wachs authored Mar 06, 2018
  
  3e88e113
- Nonexistent/unavailable harts are not halted. · 32cbb9bb
  Tim Newsome authored Mar 19, 2018
  
  32cbb9bb
- More clarification. · f8a7bb7f
  Tim Newsome authored Mar 19, 2018
  
  f8a7bb7f
Mar 17, 2018
- Merge pull request #243 from riscv/prvreset · 1360e09b
  Tim Newsome authored Mar 16, 2018
```
Change dcsr.prv reset value to 3
```
  1360e09b