1. Apr 14, 2018
  2. Apr 12, 2018
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  4. Mar 31, 2018
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  12. Mar 16, 2018
    • Tim Newsome's avatar
      Change dcsr.prv reset value to 3 · efb7e455
      Tim Newsome authored
      This will help avoid a trap where an implementation might end up with
      prv 0 when entering debug out of reset. Even in that case prv should be
      set from the privilege mode of the processor, which should be machine
      mode, but specifying this as the actual value makes things a little
      simpler.
      efb7e455
    • Tim Newsome's avatar
      Clarify hart array mask register size. · f19946b1
      Tim Newsome authored
      f19946b1
  13. Mar 15, 2018
  14. Mar 14, 2018
  15. Mar 13, 2018